samg
Newbie level 4
Hi,
Is it possible to trace the contents of a reg ("reg" data type in verilog) variable used inside a verilog task in Vivado simulation output?
I just want to see the changes in that reg.
Is it possible to trace the contents of a reg ("reg" data type in verilog) variable used inside a verilog task in Vivado simulation output?
I just want to see the changes in that reg.