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[SOLVED] VHDL what is possible. Can I have a package within a package

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wtr

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If I was in Verilog I could do
`include "my_defines.sv"
My defines could have multiple includes to other snippets of code. The nature of Verilog compilers allow these various includes to be pulled into the current file I'm compiling.

!!!!!!!!!!!!!!!!!!!
Now I'm curious if I can do something similar in VHDL land.

For example

Code VHDL - [expand]
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package word_type_pkg is
 
    -- Declarations
    constant c_nible_size : integer := 4;
    constant c_byte_size  : integer := 8;
    constant c_word_size  : integer := 16;
    constant c_dword_size : integer := 32;
    constant c_qword_size : integer := 64;
    constant c_oword_size : integer := 128;
 
    subtype nible_t is std_logic_vector(c_nible_size  - 1 downto 0);
    subtype byte_t  is std_logic_vector(c_byte_size   - 1 downto 0);
    subtype word_t  is std_logic_vector(c_word_size   - 1 downto 0);
    subtype dword_t is std_logic_vector(c_dword_size  - 1 downto 0);
    subtype qword_t is std_logic_vector(c_qword_size  - 1 downto 0);
    subtype oword_t is std_logic_vector(c_oword_size  - 1 downto 0);
 
end package word_type_pkg;




Code VHDL - [expand]
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package other_pkg is
-- stuff
end package other_pkg;




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use x.word_type_pkg.all;
use t.other_pkg.all;
 
package combined_pkg is
--
-- use the other package
end package;



RTL code

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
library generics;
use generics.combined_pkg.all;
 
entity ...

 

I'm not sure if you can do this or not, but it looks like a mess to me. Why not just infer each package separately? What's to be gained, other than burying some things so deep that debugging would be more difficult?
 

You are comparing apples to oranges here.

`include is a pre-processor command, like #include in C, which pretty much just copies and pasts the file as is into the same position where the `include exists. Its not a self contained package (as that would be a package in SV), but just a text file that makes up part of a larger text file.
VHDL has no pre-processor, so you cannot do this. But packages are self contained in VHDL, so I dont know why you would want to "include" a package inside another package, as VHDL has no include directive or keyword.

You can "use" a package almost anywhere, but all it does it make the package contents visible in the scope where it is used. so you can do this:


Code VHDL - [expand]
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process
  use std.textio.all;
 
begin
  -- textio stuff can only be seen in here, not outside the process
end process



But that is a question about scoping, not inclusion.

On a side note - changes to packages in VHDL 2008 allow you declare a package pretty much anywhere.
eg.


Code VHDL - [expand]
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process
  package my_package is
    constant A : integer := 1;
  end package;
 
  package body my_package is
    variable av : integer;  -- you can put in context things - so you can put variables in packages when you declare the package where a variable can be placed
  end package body my_package
begin
 
  --do so stuff
end process;



- - - Updated - - -

Vhdl 2008 also allows contexts, basically groups of packages that can be included in a single line:


Code VHDL - [expand]
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context my_context is
    library lib1;
    use lib1.pkg.foo;
    library lib2;
    use lib2.pkg.bar;
end context;
 
--And you can just put this at the top of the file instead of all the libraries
 
Context lib.my_context

 
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    wtr

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This is powerfull! Shame that most tools suc-k with 2008 compatibility.

What I found is that it is not mentioned inside a package itself, but outside.

such that

Code VHDL - [expand]
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package x is
end package x;
package y is
end package y;
package z is
--context declaration here fails
end package;
context my_context is
library my_lib;
use my_lib.x, my_lib.y, my_lib.z;
enc context;
-----------------------
library my_lib;
context my_lib.my_context;
 
entity ...stuff



It also appears that this website syntax detect doesn't recognise context either!
 

The simulators are all up to 2008 (except declaring packages in processes in Modelsim - that is not on their roadmap)
For synthesis, the only one I think has full 2008 compatability is Synplify.

To be honest, most of the 2008 changes that really bring new stuff are aimed at simulation anyway, and to try and bring it up to match to power of SV. The stuff that is useful for synthesis is just a way to reduce RSI and can all be done with 1993 code anyway.
 

Speaking about RSI.
Do you code in Vim?
Do you have an ergonomic keyboard?
 

When I wrote VHDL, I used vim. notepad++ is probably ok -- I use it for other things. In theory it offers my "big-three" features of syntax-highlighting, block-edit, and marker-based-code-folding. Although I've never been able to set up the latter because I don't use notepad++ and my only interest was getting that set up for co-workers. People tend to underestimate this amazing feature. People who don't have this feature very often write code that shows that they clearly understand this feature but don't get the benefit. While it is possible to write HDL without it, I don't see any benefit to not using it.

For that reason, I won't use notepad++ for any serious HDL development as I consider that to be a fundamental feature. It is supported in vim/emacs and when used correctly is absurdly useful. Especially if you can get a dev team that can use vim/emacs and use this style. I've had notepad++ users attempt to maintain the format, but without being able to see it they just mess it up. And again, RTL development is so well suited to marker-based code folding to the point that I consider it an essential feature of an editor used for that purpose.

The basic idea is that each part of a HDL file is a block in a block diagram and serves a logical function. it might be one line, or it might be 100 lines. Normally, it is a component instance and a process, or a process and a few assignments. It isn't syntax-based -- it is functionality based. When everything is in a defined code fold, the file appears as a table-of-contents when opened. It is very easy to see what high-level parts are in the file while hiding declarations. navigation within a file becomes very fast. Coding style verbosity becomes a non-issue. But this relies on the developers understanding this "everything is in a fold that defines the logical function" concept.

For vim, having an imap of:
Code:
inoremap jsl std_logic
inoremap jsv std_logic_vector
inoremap VV downto
inoremap << <=
will avoid a lot of the verbose coding. "js" isn't a common sequence in any language as far as I can tell and it is both-hands home-row allowing it to be typed quickly.
 
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    wtr

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I know sigasi have mapped ,, or << to <=, I found that very useful. I'm going to pinch your insert mappings ...although I have used comments with VV to indicate its talking about below and ^^ to indicate its talking about up. I'll need another shortcut for downto
 

You could use vv instead. It seems unlikely you'll use both VV and vv. For arrows like that, I had
Code:
set ve=all
map v <C-v>
and then i just pressed v, moved to where I wanted the row to end, and then "rV". ve is virtual edit and lets you move the cursor past the end of a line.
 

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