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[SOLVED] RV Layout Rules (what is RV count and RV holes in 28nm technology)

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Arokia

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in the 28nm design rule file we have a topic called "RV Layout Rules", and they have mentioned the below lines there

"Please allow sufficient RV counts to provide enough currect for EM and ESD protection. There it is recommened to put as many RV holes as possible.

My question is what are "RV counts" and "RV holes" and how are they realted to EM (electromigration) and ESD (Electrostatic discharge).

Thanks,
Arokia.
 

Sounds like "RV counts" and "RV holes" are the same. Generally, EM (electromigration) and ESD (Electrostatic discharge) are also the same for this discussion. Vias have a current density limit which you can find in the design rules. You need to place enough vias in your ESD devices to handle the current during an ESD event. There should be ESD devices somewhere in your PDK libraries.
 
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    Arokia

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Step back to "what the hell is "RV"?". I'm thinking this may
be a through-silicon via or something like that. Which could
have to carry substantial normal and abnormal-conditions
current especially on supply connections.
 
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    Arokia

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RV is the name of the via layer on the topmost metal in TSMC lingo. It's the via from AP to M9 or whatever is your topmost metal.
 
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    Arokia

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So then perhaps for some UBM / redistribution layer,
same concerns (i.e. don't add a bottleneck)?
 

See this paper for a typical layout of RV vias:

https://www.siliconfrontline.com/wp...e-for-Verification-of-Metal-Interconnects.pdf

In that case, RV was via between M10 and AP (AP is the topmost layer).

Number and locations of RV vias (as well as other vias) determine how much current is flowing through each via.
This current should be below critical/allowed value - for electromigration (EM), and for ESD test.
Critical current densities are different for EM and for ESD (ESD has much shorter time scale vs EM effect, and hence critical currents are much larger for ESD than for EM).
 
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    Arokia

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