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Rules of Thumb or Recipe for Setting Input and Output Delays + Propagation Delay

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csarami

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Hi,

On page https://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/ we read that

Code: 
In short,
set_input_delay -clock … -max … : The maximal clock-to-output of the driving chip + board propagation delay
set_input_delay -clock … -min … : The minimal clock-to-output of the driving chip. If not given, choose zero (maybe a future revision of the driving chip will be manufactured with a really fast process)
set_output_delay -clock … -max … : The t_setup time of the receiving chip + board propagation delay
set_output_delay -clock … -min … : Minus the t_hold time of the receiving chip (e.g. set to -1 if the hold time is 1 ns).

Note that if neither -min or -max are given, it’s like two assignments, one with -min and one with -max. In other words: Poor constraining.

It is emphasizing that we must Always constraint both min and max.

Screen Shot 2017-10-22 at 10.18.41 AM.png

Assuming above scenario ( picture attached above). What is the formula for setting min and max constraint for my chip in the middle in terms of the timing requirements receiving chip and driving chip?

How do we calculate the propagation delay of our chip?

I do appreciate it if you clarify this.

CS
 

csarami said:
Hi,

On page https://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/ we read that


CS
Click to expand...

I just got it. The post corresponds to FPGA. The answer to ASIC is very simple and is common sense. min input_delay for receiving module ( ( say HDL module))= min of all output delays from the last flip flop of the connecting modules to the inputs of the receiving module, etc. So in the case, one would need to draw the design and find the input and outputs of the connecting module.
 

csarami said:
I just got it. The post corresponds to FPGA. The answer to ASIC is very simple and is common sense. min input_delay for receiving module ( ( say HDL module))= min of all output delays from the last flip flop of the connecting modules to the inputs of the receiving module, etc. So in the case, one would need to draw the design and find the input and outputs of the connecting module.
Click to expand...

you are right and wrong. what you said applies for block design, where you will be interfacing with blocks created by other people and you don't know how late signals arrive and how much load you have. most blocks will provide only sequential outputs, so the criticality of this is small -- if any.
the typical use case for these sdc constraints is for chip level constraints.
 

ThisIsNotSam said:
you are right and wrong. what you said applies for block design, where you will be interfacing with blocks created by other people and you don't know how late signals arrive and how much load you have. most blocks will provide only sequential outputs, so the criticality of this is small -- if any.
the typical use case for these sdc constraints is for chip level constraints.
Click to expand...

Thank you very much. I guess, I will understand this fully after I gain real experience with them:)
 

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