alexandicity
Newbie level 6
Hi all,
I'm trying to program an FPGA - a Proasic3 - via JTAG from a LCPS programmer (functionally equivalent to a Flashpro3).
When all wired up to the header, I start the programming process. The reading of the device IDCODE and other status data works fine (at least, I get consistent and sensible values - including a correct value of previous programming cycles).
Then I try to program. The first part of this is a chain scan, which fails. To me, all indications suggest a signal integrity issue.
The error I get from the programmer is:
Error: programmer '77435' : Signal Integrity Failure
Integrity Check Pattern Not Found.
Integrity Check Pattern :
550FAAF000FF0000FFFF
IrScan Error.
Possible chain exceeds expected maximum device count: 256.
Chain Analysis Failed.
Error: programmer '77435' : Data Bit length : 8272
Error: programmer '77435' : Compare Data : 41550F0AFFFF00FFFF0000FF0000FF00FF00FF00FF00FF0000FFFFFFFFFFFFFFFFFFF(lots more FF)
Error: programmer '77435' : Scan Chain FAILED.
Error: Failed to run Action.
Seems to be that the device's JTAG controller is getting into a weird state. Interestingly, it looks like the compare data (TDO, I assume) is consistent between attempts, suggesting it's not just some random event causing this.
Looking at the signals, I see good rises and falls, but a lot of overshoot. I fear that the overshoot is occasionally sufficient to corrupt the message. I hack around this by setting my scope probes to 1X and therefore introducing some 100pF capacitance. This makes the signals much cleaner (even if I feel dirty for doing so). When I set this, I can get the boundary scan to pass and the process to move into the erase and programming steps But this fails too, on verify, with error code 11 or -24 (indicating bad signal integrity, Vjtag or Vpump). Supply sounds like a likely candidate - during erase/programming, I see no current draw on either, which is very wrong. I assume that it is not actually doing any programming, and that more likely device's JTAG controller is still getting into a weird state.
Vpump is 3.3V and has a local 0.01uF and 0.22uF near the package pin. Vjtag, along with Vcc and Vcci, are 1.5V. Both look very stable and clean on the board near the package throughout, so I don't *think* it's a problem with these themselves. TCK is running at 1MHz, which seems to be its lowest setting. I have a 20cm wiring harness running between programmer and device, and it is possible that something is mis-wired or poorly connected (although I have checked both!) The programmer is quite happy programming an IGLOO device on a starter board.
Any thoughts as to what might be going on? Is there ever a situation where you need to add capacitance to JTAG lines? What might I be able to do to debug this further?
I'm trying to program an FPGA - a Proasic3 - via JTAG from a LCPS programmer (functionally equivalent to a Flashpro3).
When all wired up to the header, I start the programming process. The reading of the device IDCODE and other status data works fine (at least, I get consistent and sensible values - including a correct value of previous programming cycles).
Then I try to program. The first part of this is a chain scan, which fails. To me, all indications suggest a signal integrity issue.
The error I get from the programmer is:
Error: programmer '77435' : Signal Integrity Failure
Integrity Check Pattern Not Found.
Integrity Check Pattern :
550FAAF000FF0000FFFF
IrScan Error.
Possible chain exceeds expected maximum device count: 256.
Chain Analysis Failed.
Error: programmer '77435' : Data Bit length : 8272
Error: programmer '77435' : Compare Data : 41550F0AFFFF00FFFF0000FF0000FF00FF00FF00FF00FF0000FFFFFFFFFFFFFFFFFFF(lots more FF)
Error: programmer '77435' : Scan Chain FAILED.
Error: Failed to run Action.
Seems to be that the device's JTAG controller is getting into a weird state. Interestingly, it looks like the compare data (TDO, I assume) is consistent between attempts, suggesting it's not just some random event causing this.
Looking at the signals, I see good rises and falls, but a lot of overshoot. I fear that the overshoot is occasionally sufficient to corrupt the message. I hack around this by setting my scope probes to 1X and therefore introducing some 100pF capacitance. This makes the signals much cleaner (even if I feel dirty for doing so). When I set this, I can get the boundary scan to pass and the process to move into the erase and programming steps But this fails too, on verify, with error code 11 or -24 (indicating bad signal integrity, Vjtag or Vpump). Supply sounds like a likely candidate - during erase/programming, I see no current draw on either, which is very wrong. I assume that it is not actually doing any programming, and that more likely device's JTAG controller is still getting into a weird state.
Vpump is 3.3V and has a local 0.01uF and 0.22uF near the package pin. Vjtag, along with Vcc and Vcci, are 1.5V. Both look very stable and clean on the board near the package throughout, so I don't *think* it's a problem with these themselves. TCK is running at 1MHz, which seems to be its lowest setting. I have a 20cm wiring harness running between programmer and device, and it is possible that something is mis-wired or poorly connected (although I have checked both!) The programmer is quite happy programming an IGLOO device on a starter board.
Any thoughts as to what might be going on? Is there ever a situation where you need to add capacitance to JTAG lines? What might I be able to do to debug this further?