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[SOLVED] [moved] Delaying a square signal

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Wheatley

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Hi,

I want to delay a variable-frequency square signal for about 50-100 us (too much time for implementing it with inverters). How can I do this? Maybe some kind of D-latch with other stuff?

Thanks!

PD: I don't have access to digital design-synthesis-P&R tools, so the design have to be implementable with analog layout tools.
 

Re: Delaying a square signal

Hi,

Maybe an RC as delay circuit and a comparator for pulse forming could do the job.

Klaus
 

Re: Delaying a square signal

Hi,

Maybe an RC as delay circuit and a comparator for pulse forming could do the job.

Klaus

Hi Klaus,

I think that the delay time is quite long for an RC-delay. It would probably requiere a MOhm resistor and I am looking for a fully integrated solution.

Thanks!
 

Re: Delaying a square signal

Hi,

with 50% VCC as comparator threshold (for equal rising and falling edge delay) you get: delay = (0.693 x R x C).

What values you use for R and C is your decision.
For a lower value R use a higher value C.

Klaus
 

Re: Delaying a square signal

Hi,

with 50% VCC as comparator threshold (for equal rising and falling edge delay) you get: delay = (0.693 x R x C).

What values you use for R and C is your decision.
For a lower value R use a higher value C.

Klaus

That's my point. For a 50 us delay with 2 a pF capacitor, one would need a 36 MΩ resistor (quite big to be integrated with standard high-res poly).
 

Re: Delaying a square signal

Hi,

then you posted in the wrong section. I´ll move it to the "Analog Integrated Circuit (IC) Design, Layout and Fabrication" section.

Klaus
 
Re: Delaying a square signal

Hi,

then you posted in the wrong section. I´ll move it to the "Analog Integrated Circuit (IC) Design, Layout and Fabrication" section.

Klaus

Sorry!!

Thanks for your help.
 

Depending on your process, 36Mohm is not entirely unreasonable if you bias an active resistor.
 

Depending on your process, 36Mohm is not entirely unreasonable if you bias an active resistor.

Well this circuit is intended for tuning a 1 G٠active resistor. Using an RC+comparator delay would be an endless loop ��
 

Yeah, but the thing is, you can still use this if you don't really care too much about the accuracy of that active resistor (as long as the delay tolerance is acceptable to you). You could just bias it crudely using a dc gm biaser that tracks PVT.
 

Current starved inverters with per-stage capacitor loads
and resquaring buffers, are a common approach to DLL
(the RO / delay element). You need to think about how you
are going to maintain duty cycle fidelity, if you care about
that. I recommend you use inverting stages of uniform
design, noninverting stages accumulate duty cycle
distortion while inverting ones cancel.
 

I solved this issue with a fully digital circuit made up of a binary counter and a simple FSM. If I have time I'll upload a document just in case anyone has a similar problem.

Thanks!
 

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