Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

set_transition_delay interpretation

Status
Not open for further replies.

kaushikrvs

Member level 5
Joined
Jan 27, 2017
Messages
82
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
613
1. What happens if we give a high value for set_transition_delay -min and a low value to set_transition_delay -max ?? Simply if max transition delay is less than min transition delay , what would the tool do ?
2. What happens if I give a negative transition time , how would synopsys DC handle it ?
 

You could try it out with a toy example and find out. I can't understand how a signal can have a negative transition time. Slopes are either perfect (0 timing) or have a positive transition.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top