Question on simulating LO leakage for a transmitter

Dear all,

I am wondering how to simulate the LO leakage of a transmitter, I tried transient and DFT to get the spectrum, while the results are too far away from the measurement. so could anyone tell me how to simulate such performance, by which analysis.

Thanks in advance,
abcyin

You have to include device miss match and parasitic effects of layout.

pancho_hideboo said:

You have to include device miss match and parasitic effects of layout.

Click to expand...

Thanks for your reply,

The simulation is with layout parasitics and mismatch is also included, the simulation shows that a -50dB LO rejection could be achieved, while turns out to be -20 after measurement.

abcyin

abcyin said:

Thanks for your reply,

The simulation is with layout parasitics and mismatch is also included, the simulation shows that a -50dB LO rejection could be achieved, while turns out to be -20 after measurement.

abcyin

Click to expand...

Device Mismatches and Layout Parasitics are not solely sufficient.They are main contributors but some others are also contributors such as EM leakage in the package.( If you do a RFIC design)
EM influence over inputs/outputs may sometimes be dominant compare to "electrical" ones and it's quite -unfortunately- difficult to predict this effect.
A 3D EM simulation-if applicable- may help to identify but it's really hard..

Also, 50dBc LO rejection is not practically realizable.35-40 dBc is acceptable.If you use IQ modulation ( I don't know what type ) Gain and Phase Balancing between the base-band signals impact the LO rejection ( and side-band rejection too). But I don't know the case..

BigBoss said:

Also, 50dBc LO rejection is not practically realizable.35-40 dBc is acceptable.If you use IQ modulation ( I don't know what type ) Gain and Phase Balancing between the base-band signals impact the LO rejection ( and side-band rejection too). But I don't know the case..

Click to expand...

Thanks for your reply,

the spec for LO rejection is larger than -30dBc, thus I'm expecting a 40dBc from the simulation.

The TX is a BPSK modulation without IQ, the LO phase is selected by the baseband digital signals, thus I think DC offset at IF is the main cause for LO leakage. what do you think. And the main problem is what kind of simulation could give me a relatively correct result?

Thanks,
abcyin

I don't think package affects LO leakage.
Package affects isolation severely.

I can not believe 50dbc leakage, if you include Missmatch appropriately.
How do you include device mismatch ?

I think LO is quadrature phase, 0, 90,180,270.
How do you generate in your simulation ?

pancho_hideboo said:

I don't think package affects LO leakage.
Package affects isolation severely.

I can not believe 50dbc leakage, if you include Missmatch appropriately.
How do you include device mismatch ?

I think LO is quadrature phase, 0, 90,180,270.
How do you generate in your simulation ?

Click to expand...

the mismatch process is included in the simulation by selecting the mc process corner of the model, I could get some worst case with 40dB leakage by montecarlo simulation.

And the LO is generated by a divider /2, only 0 and 180 phase is selected and transmitted as we use BPSK modulation.

Thanks in advance.

abcyin said:

the mismatch process is included in the simulation by selecting the mc process corner of the model, I could get some worst case with 40dB leakage by montecarlo simulation.

Click to expand...

Can it reflect Missmatch regarding distance between devices ?

abcyin said:

And the LO is generated by a divider /2, only 0 and 180 phase is selected and transmitted as we use BPSK modulation.

Click to expand...

Does layout parasitc extraction include R and C ?
Especially regarding divider and LO path to mixer.

I'd guess this is either on an eval board / COB or at a
probe station. Neither one can be ignored as the sims
probably have been doing. Do you have de-embed
units, boards, etc. to validate your test setup, and
have done?

LO circuit activity may kick the ground enough to show
up in the output by the ground loop. Inductances on a
ground or power shared by LO and PA can be coupling
points. How well is this represented?