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[Moved] Combinational loop synthesis

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kaushikrvs

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I know that combinational loops are inveterately considered as a bad design ? but I have seen few designs which employed combinational loops and have worked well on the silicon too.... For example, a controllable ring oscillator... So is it ok to have combo loops in the design ? what are the consequences of doing it or to be precise what are the limitations for wmploying it ?
 

Re: Combinational loop synthesis

You should only use them if you deliberately intend to use them. Loops will inevitably oscilate, hence their use in a ring oscillator. But the problem with something like that is the timing on them is non deterministic, varying with process (chip to chip differences), voltage and temperature.

Otherwise, they are not really much use and usually occur from poor design. There are much better options than ring oscillators for commercial designs. Your example would only be a hobby project.
 

Re: Combinational loop synthesis

Thanks for the reply.. but are you saying that they are not used in a real SOC ? because Ive seen them using it and making them don't touch during synthesis process?
 

Re: Combinational loop synthesis

Are you talking about FPGA socs or ASICs?
On an FPGA, they are still likely to be hobby projects, I doubt any serious commercial designer would use one.
I dont know enough about ASICs to say either way, but I would be surprised if they were used for similar reasons.
 

Re: Combinational loop synthesis

Yes ASICS, they've used the ring oscillators using the combo loop logic and as I said, it works on silicon without an issue.... However I agree that they will loose stuck-at coverage because the DFT guys will not be able to observe the stuck-at gates which are in the vicinity of this gate.....
 

Re: Combinational loop synthesis

Yes ASICS, they've used the ring oscillators using the combo loop logic and as I said, it works on silicon without an issue.... However I agree that they will loose stuck-at coverage because the DFT guys will not be able to observe the stuck-at gates which are in the vicinity of this gate.....
Click to expand...

First of all you should have posted this in the ASIC sub-forum, not here! (don't create a new thread, some mod will move it sooner or later)

Yes, they have been used successfully in ASICs. In my prev company, they had bought a TRNG (true random number generator) IP which had a ring oscillator and the SoC was successfully taped out. This was about 3-4 years ago.
 

Re: Combinational loop synthesis

Thanks for the reply..... I want to know how did that happened , how come they've taped out successfully ? My requirement is simpler I want to generate a stable combo loop , It doesn't fluctuate at all (Stuck-at kind of ckt) ? Can I go ahead to implement it and run it out without an issue ? (even on silicon)
 

Re: Combinational loop synthesis

kaushikrvs said:
Thanks for the reply..... I want to know how did that happened , how come they've taped out successfully ? My requirement is simpler I want to generate a stable combo loop , It doesn't fluctuate at all (Stuck-at kind of ckt) ? Can I go ahead to implement it and run it out without an issue ? (even on silicon)
Click to expand...

the general answer is NO, a big resounding NO. one should never allow combinational loops for generic logic.

there are exceptions from which you want to leverage the random behavior of the oscillation. it still is very unlikely you will use this as part of the logic of a system. Maybe for a special IP, like mentioned above.

I don't understand why you are obsessed with this 'how did they tapeout a combinational loop"? They did it like you do for any other circuit. Foundry doesn't care, as long as the polygons are valid, they will fab it.

I also don't understand what is that you are calling a stable combo loop. That statement is wrong by definition. Combo loops are not stable.
 

There are stable loops, an OR gate with one of its inputs controlled, and the other input is connected to output(combo loop) , so once an I/P 1 is given the OR gate gets stuck-at-1 and this is what people call as a stable loop.
 

kaushikrvs said:
There are stable loops, an OR gate with one of its inputs controlled, and the other input is connected to output(combo loop) , so once an I/P 1 is given the OR gate gets stuck-at-1 and this is what people call as a stable loop.
Click to expand...

Which is still unstable for the other condition.

Let me be very clear here. Whenever a designer is insisting that there is a reason to do a combinational loop, it strongly suggests lack of experience.
 

A DFF is comprised of two latches (= combinational loops) in master-slave configuration on the transistor level. In so far I don't understand the generalized statement about unstable combinational loops.

dff.png

Although a logic design will mostly utilize synchronous flops as storage elements, e.g. the above shown DFF macro, there are cases where transparent latches are preferred.
 

Re: Combinational loop synthesis

ThisIsNotSam said:
I also don't understand what is that you are calling a stable combo loop. That statement is wrong by definition. Combo loops are not stable.
Click to expand...

The most common non-trivial example that I know of is the ones-complement adder. In this circuit, the carry-out of the last stage is fed to the carry-in of the adder. This circuit does not oscillate continually nor does it result in a memory effect.
 

Re: Combinational loop synthesis

FvM said:
A DFF is comprised of two latches (= combinational loops) in master-slave configuration on the transistor level. In so far I don't understand the generalized statement about unstable combinational loops.
Click to expand...

That is a sequential loop, which is ok. Yet, companies will spend huge amounts of time/personnel to characterise flops. I am talking about electrical simulations (silicon smart, library characterizer, etc.) and actual characterisation silicon. The loop artifact, while being fundamentally needed, is a headache!

vGoodtimes said:
The most common non-trivial example that I know of is the ones-complement adder. In this circuit, the carry-out of the last stage is fed to the carry-in of the adder. This circuit does not oscillate continually nor does it result in a memory effect.
Click to expand...

While this circuit does work and might be useful, the reality is that you will never design it. From a CAD perspective, it is not stable. No timing engine that I know of can handle combinational loops, timing analysis needs a levelized notion of a netlist. It can't do "double pass" analysis. Also, the synthesis tools I am used to would not let this pass. Tools would either give up or insert a combo breaker.

Bottomline is, don't design digital ASICs with combo loops. They might have a place in special IP, but they have no use in random logic.
 

Bottomline is, don't design digital ASICs with combo loops.
Click to expand...
I agree as a general rule, but can't agree with the generalized statements about combinational loops being basically unstable.

That is a sequential loop, which is ok.
Click to expand...
Don't see the difference of "sequential" versus "combinational" loop. The DFF macro has combinational loops.
 

Re: Combinational loop synthesis

vGoodtimes said:
The most common non-trivial example that I know of is the ones-complement adder. In this circuit, the carry-out of the last stage is fed to the carry-in of the adder. This circuit does not oscillate continually nor does it result in a memory effect.
Click to expand...

Firstly, if we use such a combo loop , the OR gate gets stuck-high and the DFT engineers will remonstrate , because all the stuck-at-faults in the vicinity of this OR gate will not be observed. Hence, they will loose their stuck-at coverage, Plan to have a flop in between and this design will pass the litmus test.
 

Latch Synthesis and Precautions

What are the consequences of having a latch in the design , does it create a problem in the circuit ? Are they synthesizable ? If Yes, what precautions should I take to implement a latch in my design ?
 
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Re: Latch Synthesis and Precautions

kaushikrvs said:
What are the consequences of having a latch in the design , does it create a problem in the circuit ? Are they synthesizable ? If Yes, what precautions should I take to implement a latch in my design ?
Click to expand...

Timing engines prefer flop to flop timing paths. Latches break that paradigm. They can be used, but sparingly and very carefully.
 

Re: Combinational loop synthesis

kaushikrvs said:
Firstly, if we use such a combo loop , the OR gate gets stuck-high and the DFT engineers will remonstrate , because all the stuck-at-faults in the vicinity of this OR gate will not be observed. Hence, they will loose their stuck-at coverage, Plan to have a flop in between and this design will pass the litmus test.
Click to expand...

Interesting. I don't do ASIC designs so this is probably true and worth noting. The one's compliment math is the only example of a useful (ip checksum), non-memory, stable circuit that has combinatorial feedback. It doesn't have or-gates, but I'm guessing that is something added in analysis?

The 1's checksum can easily be hard-ip or done using a post-add for practical designs.

I basically echo FvM here. A combinatorial loop is not always unstable -- even if it isn't a good idea to design around this fact.
 

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