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Is there a static RTL coverage analyze tool?

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eruisi

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Hi, guru:

I wrote some RTL code, is there a quick way to tell me if there is any dead zone in the RTL w/o running any vector based Verilog simulation?

For example, if I accidentally tied clock input to a flop, I want to see some message like "The output of this flop will never toggle"

I know I can get this information from Primetime, but can we have a quick check at RTL level? If yes, what is the tool name?


Thanks
eruisi
 

You can read your RTL and snd clock definitions into DesignCompiler and without synthesys execute command check_timing/check_design.

Or you can use some lint-checker tools like SpyGlass.
 

Use any Lint tool as mentioned above.
In Synopsys VCS it is possible to enable Lint checks during RTL compilation by using a suitable switch. It is most probably also possible for Cadence tools.
 

dpaul said:
Use any Lint tool as mentioned above.
In Synopsys VCS it is possible to enable Lint checks during RTL compilation by using a suitable switch. It is most probably also possible for Cadence tools.
Click to expand...

Yes, Cadence has a lint tool called HAL.
 

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