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Synopsis design vision and generic (VHDL)

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svip

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Synopsys dedign vision and generic (VHDL)

Hello, i write and synthetize VHDL for fpga since more than 10 year but now i am new with ASIC design
I have problem during the Elaboration of my design cause the presence of generic. is there some strange procedure to use in case of generic in synopsys?
Thank you

this is a simple example, in a top level architecture i use two times this simple generic counter
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all; 
use ieee.std_logic_arith.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity generic_counter_bis is
generic(
	N_bit : natural:=8;
	hit_gen: natural:=4;
	N_reset: natural:=6
	);
port(
	clk,rst,enable:in std_logic;
	hit:out std_logic;
	output:out std_logic_vector(N_bit-1 downto 0)
	);

end generic_counter_bis;


architecture Behavioral of generic_counter_bis is
signal acc: std_logic_vector (N_bit-1 downto 0);
--constant hit_gen_1: std_logic_vector:=conv_std_logic_vector(hit_gen,N_bit); 
begin

process(clk,rst)
begin

	if rst='1' then
	acc<=(others=>'0');
	elsif clk='1' and clk ' event then
		if enable='1' then
			if acc=conv_std_logic_vector(N_reset,N_bit) then --if acc=N_reset
				acc<=(others=>'0');
				else 
				acc<=acc+1;
			end if;
		end if;
	end if;

end process;

hit_generator: process(acc)
begin
	if acc=conv_std_logic_vector(hit_gen,N_bit) then
	hit<='1';
	else 
	hit<='0';
	end if;
end process;

output<=acc;
end Behavioral;

- - - Updated - - -

I SOLVE using manual script, the GUI seems to have a bug, launching manua script all work perfectly
Is it possible?
 

Re: Synopsys dedign vision and generic (VHDL)

no one uses the GUI, so it's possible you found a meaningless bug.
 

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