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  1. #1
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    Inequality operator in VHDL

    Hi guys. I've read that the inequality operator /= can be used inside an IF statement. My scenario is if let's say ASSIGNMENT is an Integer array of 4 from 0 to 3, and if none in the array has a value of 0 let's say ASSIGNMENT = [2 3 1 1], then I would assign a certain signal a bit vector value of "00". But I am trying the inequality operator like "if ASSIGNMENT(0) /= 0 AND ASSIGNMENT(1)/= 0 . . . and so on but it's not working. Any help?

    •   Alt11th October 2017, 10:56

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  2. #2
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    Re: Inequality operator in VHDL

    but it's not working
    Useless report. As far I'm aware of it's legal VHDL syntax, otherwise you should post the respective syntax error message. We can't know why your code hasn't the intended effect if you don't show it.



    •   Alt11th October 2017, 11:09

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  3. #3
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    Re: Inequality operator in VHDL

    if you're checking that any entry in the array is 0, then why not use the equality and an OR operator?

    [syntax=vhdl]
    if A(0) = 0 or A(1) = 0 or A(2) = 0 or A(3) = 0 then
    OP <= "00";
    end if;
    [/syntax]



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