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    Xilinx ISim - Post place and route simulation

    Hello everybody,

    I have implemented a rather big design and now i am trying to do a timing simulation.
    After PAR , i have generated the post place and route model and added the testbench file to the simulation hierarchy.
    But when i try to simulate it , iSim launches without problem but i am not allowed to press Run ( it is un-clickable )

    Anyone has any idea as to why this could happen?
    Click image for larger version. 

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    Last edited by NikosTS; 10th October 2017 at 16:11. Reason: incorrect screenshot attached

    •   Alt10th October 2017, 16:08

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    Re: Xilinx ISim - Post place and route simulation

    Never used iSim as we always used Modelsim, but isn't there a limitation on design size if iSim was not purchased? I know that a full version license for iSim was a separate product license.



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    Re: Xilinx ISim - Post place and route simulation

    Actually, i was a bit impatient to post this and later saw that at that point the " Simulator is doing circuit initialization process. ".
    Now my problem is that after the initialization the simulator crashes producing the following error : " The simulator has terminated in an unexpected manner. Please review the ISim log (isim.log) for details."

    The isim.log does not say anything specific though.

    PS: I have a full version of iSim



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    Re: Xilinx ISim - Post place and route simulation

    Personally I never run netlist timing simulations or netlist functional simulations on any of my designs, unless I suspected an issue with the synthesis tools, so I've only had to do this a few times in my career. The only time gate level simulations were mandatory was back when I did ASIC designs.

    The terminated unexpectedly is problem with iSim in general, another engineer I know used iSim a lot and complained about that, just a single change of a constant in their code could result in that error appearing or disappearing.
    Vivado has similar crashes, but has definitely gotten more stable.



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    Re: Xilinx ISim - Post place and route simulation

    So you would suggest using ModelSim for the static timing simulation?
    Also, are you aware of any fast tutorial on how to do that?



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    Re: Xilinx ISim - Post place and route simulation

    Have you run an RTL simulation? Why do you want to run a timing simulation?

    12 years in the industry, plus university, and I've never run a timing sim. RTL + proper timing constraints had been good enough so far....



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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by NikosTS View Post
    So you would suggest using ModelSim for the static timing simulation?
    Also, are you aware of any fast tutorial on how to do that?
    I'm with TrickyDicky on this...

    No, I suggest not doing any kind of netlist timing simulations with Modelsim, Incisive, VCS, Aldec, icarus, iSim, or Vivado. That is unless you have this posted in the wrong section and are taping out an ASIC...

    I've been doing FPGA designs since the mid 80's and almost never did any kind of timing simulations, except in the earliest days when the timing files were always suspect, but instead of running timing simulations which could take days (not hours) we would over constrain the design by at least 10-15%. We would back off the over constraints when the timing files became more mature (accurate), but would always leave at least 5% margin.

    Once I moved to using VHDL/Verilog and synthesis tools the only time I've run timing simulations is for ASICs and to verify simulation/synthesis mismatches and synthesis errors on FPGAs. As I've already stated this has only been required a few times in my career (over 30 years). With the addition of the technology views in most FPGA vendors tools you can easily verify that your code was translated properly, if you are suspicious of a problem in synthesis.



    •   Alt10th October 2017, 19:08

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    Re: Xilinx ISim - Post place and route simulation

    Just to add - that in my only brush with an ASIC, I dont think there was even a plan to do a timing simulation - just Lots and lots of RTL verification (both UVM and formal) followed by FPGA emulation (though it all got cancelled before we even got to proper verification).
    Basically tools are good enough now that as long as you have good code practice, the synthesised design will match the RTL.

    - - - Updated - - -

    Plus Ive only ever seen 1 proper synth bug where RTL didnt match the synthesised design, and that was in a Xilinx IP block in ISE 14.7!!



    •   Alt10th October 2017, 19:27

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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by TrickyDicky View Post
    Just to add - that in my only brush with an ASIC, I dont think there was even a plan to do a timing simulation - just Lots and lots of RTL verification (both UVM and formal) followed by FPGA emulation (though it all got cancelled before we even got to proper verification).
    Basically tools are good enough now that as long as you have good code practice, the synthesised design will match the RTL.

    - - - Updated - - -

    Plus Ive only ever seen 1 proper synth bug where RTL didnt match the synthesised design, and that was in a Xilinx IP block in ISE 14.7!!
    ASIC people still do gate level simulation. It still is very useful for finding top-level connectivity issues. But in general you do trust that the synthesis output matches the RTL just fine.
    Really, I am not Sam.



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    Re: Xilinx ISim - Post place and route simulation

    Thank you both for your replies, i guess will simulate only post-synthesis model then!



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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by NikosTS View Post
    Thank you both for your replies, i guess will simulate only post-synthesis model then!
    Why? Thats what we've been telling you not to bother with. Just do an RTL simulation.



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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by TrickyDicky View Post
    Why? Thats what we've been telling you not to bother with. Just do an RTL simulation.
    I have misunderstood then, isn't post-synthesis(post translate ) simulation the same as RTL simulation?
    As options i have behavioral, post-translate, post map and post-route simulations in ISE.

    Again sorry for the questions that may be for too beginners, but i dont have much experience



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    Re: Xilinx ISim - Post place and route simulation

    Rtl = behavioral
    Really, I am not Sam.



    •   Alt10th October 2017, 21:31

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    Re: Xilinx ISim - Post place and route simulation

    Ok that clears it up. But is behavioral simulation enough for that?
    By the way, I somehow managed to run a post-route simulation and generated totally different ( wrong )results in comparison with the behavioral simulation.



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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by NikosTS View Post
    Ok that clears it up. But is behavioral simulation enough for that?
    By the way, I somehow managed to run a post-route simulation and generated totally different ( wrong )results in comparison with the behavioral simulation.
    If this happens, it will usually be because of poor coding style, with signals missing from sensitivity lists, latches etc.
    Why not post some code so we can have a look?


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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by NikosTS View Post
    Ok that clears it up. But is behavioral simulation enough for that?
    By the way, I somehow managed to run a post-route simulation and generated totally different ( wrong )results in comparison with the behavioral simulation.
    Quote Originally Posted by TrickyDicky View Post
    If this happens, it will usually be because of poor coding style, with signals missing from sensitivity lists, latches etc.
    Why not post some code so we can have a look?
    This can also occur when doing timing simulation as the netlist will have delays on the IO that don't exist in the behavioral code, which means your testbench can cause problems. The other issue is if you don't correctly use the GLBL reset net in Xilinx to reset the entire designs FFs to their reset state, emulates the after configuration state of a Xilinx FPGA. If you don't use it all FFs that are not explicitly reset will end up being X until updated with a valid input.

    Basically this boils down to post synthesis and post route simulations are a pain to be avoided.

    Quote Originally Posted by ThisIsNotSam
    ASIC people still do gate level simulation. It still is very useful for finding top-level connectivity issues. But in general you do trust that the synthesis output matches the RTL just fine.
    We did it to verify that the layout was done correctly and the back annotated SDF with all the included parasitics still resulted in the design functioning as intended. We also ran the test vector suite generated by the DFT tool to sign off on the test vectors before tape out. Not sure how much of these are done for todays ASIC designs, our largest was only 2-3 million gates.


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    Re: Xilinx ISim - Post place and route simulation

    I will check the reset of the FFs , as i have FFs that get reset not by the "global" reset signal but by changing of an inner state ( from an FSM ) ( i guess that's what is Tricky talking about when saying poor coding style ).
    The design consists of about 14 modules, so in order to make sense, i have to upload all modules and i doubt someone will go over so many lines.
    Last edited by NikosTS; 11th October 2017 at 00:08. Reason: double post



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    Re: Xilinx ISim - Post place and route simulation

    Quote Originally Posted by NikosTS View Post
    I will check the reset of the FFs , as i have FFs that get reset not by the "global" reset signal but by changing of an inner state ( from an FSM ) ( i guess that's what is Tricky talking about when saying poor coding style ).
    The design consists of about 14 modules, so in order to make sense, i have to upload all modules and i doubt someone will go over so many lines.
    No I was referring to the glbl reset that is in all the primitives that are instantiated in the netlist (post synthesis/post route VHDL/Verilog). Not some behavioral RTL code.



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