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Why is HOLD not affected by jitter?

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kaushikrvs

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Why hold is not affected be jitter?

Why is setup affected by skew and jitter, but hold is affected only by skew, not jitter?
 

Re: Why hold is not affected be jitter?

Because jitter is based on different edges of the clock and hold is analyzed on the same edge of the clock.
 

Re: Why hold is not affected be jitter?

Setup and hold are data:clock timing. If clock jitters
relative to data then you "could" see hold time as well
as setup time "noise". On the other hand almost every
FF design I've ever done or seen has finite setup but
"zero" (that is, less than zero, fuggedaboudit) hold time.

I guess my point there is that just because you don't
see, or aren't presented, a hold-time-jitter criterion
doesn't mean there is no effect. It may just mean the
hold time is -100pS +/- 10pS, rather than -100pS
period. So maybe 0 hold time buries either case and
it's one less constraint to bother the synthesis for
no upside.

When you're pushing the limits of a technology to
the point that you have to design clocked data paths
in Spectre / SPICE with layout parasitics, and up
against the FF+logic delay vs clock period per stage,
you will worry about clock jitter because setup time
is clock->data(clock)->clock. Same should be true of
hold, but you seldom run into hold time issues if there
is significant data delay from clock.
 

Re: Why hold is not affected be jitter?

dick_freebird said:
Setup and hold are data:clock timing. If clock jitters
relative to data then you "could" see hold time as well
as setup time "noise". On the other hand almost every
FF design I've ever done or seen has finite setup but
"zero" (that is, less than zero, fuggedaboudit) hold time.

I guess my point there is that just because you don't
see, or aren't presented, a hold-time-jitter criterion
doesn't mean there is no effect. It may just mean the
hold time is -100pS +/- 10pS, rather than -100pS
period. So maybe 0 hold time buries either case and
it's one less constraint to bother the synthesis for
no upside.

When you're pushing the limits of a technology to
the point that you have to design clocked data paths
in Spectre / SPICE with layout parasitics, and up
against the FF+logic delay vs clock period per stage,
you will worry about clock jitter because setup time
is clock->data(clock)->clock. Same should be true of
hold, but you seldom run into hold time issues if there
is significant data delay from clock.
Click to expand...

I am very confused by this. I think you are talking about hold timing and setup timing as being properties of a flipflop. And you are right, these numbers are never zero. I have seen numbers like 3-5ps for FF hold in modern finfet technologies. However, I believe OP is asking about why clock jitter doesn't appear in his timing report when he does setup analysis vs hold analysis. The answer ads-ee gave is correct, jitter on the clock makes no difference for hold purposes, as it is effectively a one clock edge property.
 

Re: Why hold is not affected be jitter?

well it matter for multi cycle paths....
 

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