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    Regarding connections in a CPLD schematic

    Hi,

    I was planning to make a CPLD based hardware (for the first time :) ) and was going through the schematic of a Digilent board here:


    I have the following queries pls:

    The global output enable pins (2,3,5,6) are connected as general I/O pins in connector JI. So if I wanted to enable/disable all I/O pins of the IC, how could I do so? Just guessing but if I connect 3.3 v or GND to these pins, will it not enable/disable all I/Os (and the pins wont function as general I/Os)?

    Global Set/Reset pin no. 143 is connected to VCC3v3/GND using an SPST (net label BTN0). But when the SPST is closed for GND connection, will it also not provide a direct path between VCC3v3 and GND (through a 4K7 resistor)? Is it not better to use a SPDT with a 10K resistor in series with central pin and VCC3v3 on one side and GND on other side of the SPDT? Also, what is this BTN1 (connected to pin no. 94)?

    Clock divide reset (pin no. 35) is connected to port C of Atmel 90USB162 IC. Suppose I don’t want USB interface. Can I put a manual switch instead (for eg. a SPDT switch to connect the pin to either VCC/GND for enabling/ disabling the function)? If not, what are the work arounds?

    Similarly, for what purpose is pin 124 (net label SW1) connected to an SPDT (to toggle between VCC3v3/GND—if so, the reason thereof)? Similarly why is pin 125 (net name MEM1) connected to 1 kB EEPROM (maybe for some kind of security purpose). If I don’t want to use it, ie. I don’t want any security feature, I hope, the I/O pin is free for general usage. And finally where is pin 95 connected to (net name REG_RST)?

    The unused I/O pins have been kept floating (the ones like pin no. 131, 132 etc). Is it the standard policy? Someone told me it contributes to power wastage in I/O blocks (internally). Is it true?

    Finally, what are functional blocks and I/O banks. Where can I know about them and what things should I keep in mind while making the PCB for the CPLD.

    Looking forward to your kind help.

    Thanking You,
    Arvind Gupta.

    •   Alt10th October 2017, 12:19

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  2. #2
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    Re: Regarding connections in a CPLD schematic

    Hi,

    You are talking about XILINX XC2C256?

    You urgently need to read all related datasheets. A couple of documents. Boring, but necessary.

    Your questions:
    Global Enable: They are configurable. You donīt need to use them, but you may use them.
    On the other hand you could use any other GPIO to switch any desired output(s) to three sate.

    EEPROM:
    Donīt use it if you donīt need it. I donīt think this is for security ... itīs general purpose.

    Global Set/Reset:
    Also configurable.
    The circuit is the common pull-up concept. It is very basic. Iīd prefer it against a SPST. No need to worry or change anything.
    The only drawback is the 700uA additional current when pulled down.

    Floating pins:
    No. Donīt leave them floating. But you may kee them unconnected. It is a programming feature. You can select how they are treated. Either globally or individual. Truely floating (not recommended), pull-up, bus-keeper..

    I/O bank:
    Each bank may have different I/O voltage. If you have different signal levels, then you have to take care. If all I/O have the same levels you donīt need to take care.

    Functional blocks:
    Itīs important for very complex designs. Usually itīs better to keep a complex circuit within one FB, because the interconnectins are more flexible. The count of signal lines between different FB is limited.

    Own design:
    Do simne tiests with the digilent board. Different applicatons. Just play around with it to get familiar. I donīt recommend to make a PCB for your first CPLD project.
    Go step by step.

    Klaus


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    •   Alt10th October 2017, 13:11

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    Re: Regarding connections in a CPLD schematic

    OK. Thanks. I have been tinkering with development boards for some time. Hence was thinking of venturing out to make something. Some questions in the original post still remain though

    1. Any ideas what is this BTN1 in the schematic. Does everyone need it. Similarly where is pin 95 going to (net name: REG_RST) and what is the purpose of the connections of pin 124 (net name: SW1)?

    2. If I used a SPDT for global set / reset, is it ok? Is a 10K series resistor enough?

    3. What about the clock divide issue mentioned in the original post. Where did this Atmel chip gain entry into a spartan board.

    4. You mentioned that the global signals (enable, set/reset etc) are configurable. How pls. ie. how do I configure them. Do I have to configure a CPLD IC once before starting to use it or every time when I configure the IC to work like the required hardware ?

    5. Excuse my ignorance but what is the difference between leaving a pin unconnected (which is OK) and truly floating (which is not OK; as mentioned in your post). And thanks again.

    Regards,
    Arvind Gupta



    •   Alt10th October 2017, 16:21

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    Re: Regarding connections in a CPLD schematic

    This statement still applies, resolve that and many of your answers will magically be solved...
    Quote Originally Posted by KlausST View Post
    You urgently need to read all related datasheets. A couple of documents. Boring, but necessary.
    5. unconnected pins are floating unless configured to not float, e.g. having a weak pullup internal to the device.



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    Re: Regarding connections in a CPLD schematic

    Hi,

    to 4)
    a picture says more than 1000 words...
    Click image for larger version. 

Name:	CPLD_setup.png 
Views:	5 
Size:	39.5 KB 
ID:	141738

    to 5)
    If a signal has an internal pullup, pulldown or a keeper, then the signal is not floating and you may leave it unconnected (if not used).

    Klaus



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    Re: Regarding connections in a CPLD schematic

    Hi ads-ee, KlausST,

    Thanks for your replies. I checked Xilinx database. It has more than 50 application notes, several user guides & white papers related to Coolrunner II CPLDs. So kindly point me to the related documents necessary to answer my queries in post #1.

    One more thing, I checked the process properties --> Fitting option. Here the I/O voltage standard is default to LVCMOS18. If I use 3.3v supply as VCCIO in hardware, will it automatically detect the same and change the option / I have to manually change the option to 3.3v or will it display an error during programming ?

    Thanking You,
    Arvind Gupta



    •   Alt11th October 2017, 05:54

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    Re: Regarding connections in a CPLD schematic

    Hi,

    You should set up I/O levels.
    Either globally in the fitting options, or individually in the code/schematic or individually in the UCF file.

    About the datasheets.
    You need to read through all the datasheets and those documents that describe timing, I/O behaviour, power supply, programming and other basic stuff...
    And I recommend to open all the others and read at least the first page to get a clue what they are talking about...so that you can decide if they are of interest for your current application.

    I assume sooner or later you need to go through almost all documents. Don't hurry...time will tell.

    Klaus



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