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    Trigger Signal in VHDL

    Hello guys! I think this is a basic question but I hope you can help me.

    For example, I have a signal DONE that will be high for a certain time for 1 clock cycle. How can I create a signal that is same with DONE and will occur exactly after DONE and also 1 clock cycle. Thank you.

    •   Alt9th October 2017, 15:25

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    Re: Trigger Signal in VHDL

    a delayed version of the DONE in the following clock cycle just requires a register (flip-flop) on the DONE signal producing an output that is exactly the same but delayed a single clock cycle.

    Based on this and other questions you should focus on learning logic design first. You don't seem to have a firm grasp on the fundamentals of digital design.



    •   Alt9th October 2017, 15:29

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    Re: Trigger Signal in VHDL

    If I implement the code, TSS_TRIGGER is just the same with TSS_DONE during the clock cycle. TSS_DONE gets high only for one clock cycle and then goes back to zero. What I want to happen is when TSS_DONE gets high for a clock cycle, on the next clock cycle, a signal will get high for that clock cycle (TSS_DONE is low already). So it's like I'll get a copy of TSS_DONE but with a dealy of one clock cyle. But the code below only copies TSS_DONE. They are both high at the same clock cycle.

    Code:
    TRIGGER0: PROCESS(CLK)
    	BEGIN
    	IF(CLK'EVENT AND CLK='1')THEN
    		--IF (TSS_DONE = '1') THEN
    			TSS2_TRIGGER <= TSS_DONE;	
    		--END IF;
    	END IF;
    	END PROCESS TRIGGER0;



    •   Alt10th October 2017, 13:01

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    Re: Trigger Signal in VHDL

    No - TSS2_TRIGGER will be a 1 clock delayed version of TSS_DONE.



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    Re: Trigger Signal in VHDL

    Hi,

    I´m not familiar with VHDL.
    But I wonder if ever TSS2_TRIGGER can become '0' after it was set to '1'?

    For a one clock_cycle_delay id expect this code:
    Code:
    TRIGGER0: PROCESS(CLK)
    	BEGIN
    	IF(CLK'EVENT AND CLK='1')THEN
    		TSS2_TRIGGER <= TSS_DONE;	
    	END IF;
    	END PROCESS TRIGGER0;


    Klaus



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    Re: Trigger Signal in VHDL

    Quote Originally Posted by KlausST View Post
    But I wonder if ever TSS2_TRIGGER can become '0' after it was set to '1'?
    Yes it can, because the enable signal is commented out.
    But you are correct, with fully uncommented code, assuming TSS2_TRIGGER powers up to 0, then it is a latch.



    •   Alt10th October 2017, 13:40

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    Re: Trigger Signal in VHDL

    Hi,

    Aaah the "--" is the sign for a comment. This makes sense.

    Thanks



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