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    Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    The BFMs are used to help with verification of Qsys components being written by the developer. Is this true?

    If so, then must one know SystemVerilog to use them? Do they fully support VHDL?

    •   Alt9th October 2017, 10:54

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    Re: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    Most Verilog/SV components can be instantiated in VHDL. So no, you dont need to know SV to use them, but you will need a simulator/Licence that Supports SystemVerilog and Mixed Mode simulation.


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    •   Alt9th October 2017, 11:01

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    Re: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    I have not used BFM yet since I thougt that SystemVerilog is required as they are written in SystemVerilog and I have no idea how they can be used from VHDL testbench.

    Anyway, is it also not possible that a person write some functions in VHDL to wiggle and the signals and test the output of the block rather than use BFM? How exactly do BFMs make life easy?



    •   Alt12th October 2017, 10:24

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    Re: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    Anyway, is it also not possible that a person write some functions in VHDL to wiggle and the signals and test the output of the block rather than use BFM?
    Surely you can write your own VHDL test-bench but that will cost time and time = money.

    How exactly do BFMs make life easy?
    By providing you with an environment (assuming that functionality of the BFM is guaranteed) that makes monitoring and reporting of signals easier (C style coding) when compared to conventional RTL style coding.

    You might want to take a look at these BFMs from http://syswip.com/ and then integrate them into a VHDL/Verilog TB. If you do so for one design you will get a feel of how the life of a logic designer engineer becomes easier.
    .....yes, I do this for fun!



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    Re: Must one known SystemVerilog to use Avalon Interface Bus Functional Models?

    Quote Originally Posted by matrixofdynamism View Post
    I have not used BFM yet since I thougt that SystemVerilog is required as they are written in SystemVerilog and I have no idea how they can be used from VHDL testbench.

    Anyway, is it also not possible that a person write some functions in VHDL to wiggle and the signals and test the output of the block rather than use BFM? How exactly do BFMs make life easy?
    Of course you can do this? but how do you verify that your BFM (which is what you create with your pin wiggles) meets the Spec of the interface you are driving?
    The point of the supplied BFMs is that you should be fairly confident that they meet the spec of the interface you are driving. They should also allow you to input transactions and not worry about the pin wiggling. eg all you ask for is "Write X to address Y", without having to worry about the correct sequence of pin wiggles to acheive this, as this is handled inside the BFM.

    In this case, the BFM is provided in SV as this natively supports randomisation and has the infrastructure required to set this up (eg. classes, interfaces, virtual interfaces etc). But most of this can also be achieved in VHDL with VHDL2008, with randomisation coming from OSVVM. The reason it is supplied as SV is that it has been around since 2005, and VHDL2008 (and OSVVM) support is only really now arriving, and so the majority of verification has been done in SV, and now it is all written in SV, people dont want to re-write it for VHDL.



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