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    Xilinx ISE problem - Congested design results in failed routing

    Hello everyone,
    Im implementing a LDPC ( low density parity check ) decoder on ML605 evaluation platform ( the device is a large Virtex6 ).
    After synthesis step, the resources used according to the report is 29% Registers and 61% LUTs with an actual ratio of 83.
    After the map process, these resources decrease even further, leading the LUTs needed to only 50-52%.
    The problem is that , at the PAR step, the router detects "a dense , congested design" and therefore stops leaving around 90k nets unrouted.

    Any suggestions on how i can overcome that? The resources needed are not so extreme i think.
    Note that i havent used any constraints on the clock frequency, neither have i done any floorplanning.

    Thank you in advance,
    Nikos

    •   Alt7th October 2017, 16:05

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    Re: Xilinx ISE problem - Congested design results in failed routing

    Note that i havent used any constraints on the clock frequency, neither have i done any floorplanning.
    Is the design properly constrained?
    Very difficult to guess the cause with so little info.
    .....yes, I do this for fun!



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    Re: Xilinx ISE problem - Congested design results in failed routing

    As the synthesis report shows nearly 2x LUT to FF usage seems to indicate you didn't think much about pipelining the design. Probably some really large combinational circuits between register stages that have large fanouts. Multiple instance of such logic and potential coding of feedback loops (latches) can have detrimental effects on a design. Without significantly more detail on the design (the coding) and the report files from synthesis not much help can be given.

    ISE has always had a problem with packing things too closely together when placing a design. Sometime you would actually have to floorplan by disallowing the usage of every other column of Slice/CLBs to help alleviate congestion.



    •   Alt9th October 2017, 22:41

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    Re: Xilinx ISE problem - Congested design results in failed routing

    Hello and sorry for the late replies.
    @dpaul
    As i am fairly new to using ISE, could you explain to me what constraints do you mean? I haven't included any .ucf file on my hierarchy.

    @ads-ee
    The only big combination circuit that i have included , is a barrel shifter that doesn't use any registers between the multiplexer stages. Apart from that , i think every other output is registered.
    Would an upload of the synthesis report help?

    Thank you



    •   Alt10th October 2017, 12:15

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    Re: Xilinx ISE problem - Congested design results in failed routing

    Quote Originally Posted by NikosTS View Post
    Hello and sorry for the late replies.
    @dpaul
    As i am fairly new to using ISE, could you explain to me what constraints do you mean? I haven't included any .ucf file on my hierarchy.

    @ads-ee
    The only big combination circuit that i have included , is a barrel shifter that doesn't use any registers between the multiplexer stages. Apart from that , i think every other output is registered.
    Would an upload of the synthesis report help?

    Thank you
    At the absolute minimum you should include clock constraints and pin location constraints.



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    Re: Xilinx ISE problem - Congested design results in failed routing

    Quote Originally Posted by ads-ee View Post
    At the absolute minimum you should include clock constraints and pin location constraints.
    You mean frequency constraint for the clock, and grouping ( let's say ) all the output pins and all the input pins ?



    •   Alt10th October 2017, 14:44

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    Re: Xilinx ISE problem - Congested design results in failed routing

    Quote Originally Posted by NikosTS View Post
    You mean frequency constraint for the clock, and grouping ( let's say ) all the output pins and all the input pins ?
    Yes the frequency constraint (that is what a clock constraint means).

    Grouping?
    Pin locations and the IO standard used for all pins. Gives some guidance to the tools where to put pins, otherwise I've seen ISE put pins for a bus on opposite sides of the die!.

    As I said ISE has a really poor placer. On dense high clock frequency designs with lots of RAM blocks I've regularly had to run smartxplorer runs with effort levels on high to get one run that would make timing and then export all the locations of BRAMs and DSPs to use as a constraint for the subsequent runs. ISE has a much easier time of placing logic when the RAMs and DSPs are locked down.



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    Re: Xilinx ISE problem - Congested design results in failed routing

    Thanks for your reply, i will have a close look on pin constraints.
    The design indeed uses many block rams ( 216 to be exact ), so i guess the problem lies there?

    - - - Updated - - -

    One last question though; if i dont put any constraint on the clock, the placer/router will not try to implement the design with the highest possible frequency?



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    Re: Xilinx ISE problem - Congested design results in failed routing

    I've never had any luck with using no clock constraint it usually just makes ISE do a worse job. Sometimes it seems like ISE uses 1GHz as the clock constraint, given the amount of effort it uses and then gives up (as it was unrealistic to begin with).

    Give a clock constraint even if it is unrealistically low just as a quick check on what the design performance might be (extra positive slack margin).



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    Re: Xilinx ISE problem - Congested design results in failed routing

    Ok i understand, thank you very much for your time!



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