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    Pipeline problem VHDL

    Hi guys! I need some help.

    Here is the scenario, in the first timeslot (or one cycle), a value is outputted. Then on the next timeslot, the same signal but it is already updated to anew value. What should I do so that I can use the value from the first timeslot during the second timeslot. Take note that on the second timeslot, the value changes already but what I need is the value from the previous timeslot. Am I gonna store it? How? Help please. newbie here in VHDL. Thanks.

    •   Alt6th October 2017, 16:24

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    Re: Pipeline problem VHDL

    Quote Originally Posted by nizdom View Post
    Am I gonna store it? How? Help please. newbie here in VHDL. Thanks.
    VHDL is a hardware description language, how do you store a value for later use (next clock cycle) in hardware?....

    use a flip-flop.

    input -- DFF -- output

    output is delayed by 1 clock



    •   Alt6th October 2017, 16:29

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    Re: Pipeline problem VHDL

    Quote Originally Posted by ads-ee View Post
    VHDL is a hardware description language, how do you store a value for later use (next clock cycle) in hardware?....

    use a flip-flop.

    input -- DFF -- output

    output is delayed by 1 clock
    What kind of flip flop should I use? Thaanks!



    •   Alt6th October 2017, 16:34

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    Re: Pipeline problem VHDL

    Quote Originally Posted by nizdom View Post
    What kind of flip flop should I use? Thaanks!
    I already showed DFF i.e. D Flip-flop. I'm not going to post the truth table, go look it up in google.



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    Re: Pipeline problem VHDL

    Hi,

    Here is the scenario, in the first timeslot (or one cycle), a value is outputted.
    I wonder how the output comes at first...

    Isn´t it usually this order:
    input --> processing --> output?

    **
    Without knowing what "value" format and what timeslot you are talking about .. the answer can only be very vague.

    Klaus



    •   Alt6th October 2017, 16:36

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    Re: Pipeline problem VHDL

    Quote Originally Posted by nizdom View Post
    Hi guys! I need some help.

    Here is the scenario, in the first timeslot (or one cycle), a value is outputted. Then on the next timeslot, the same signal but it is already updated to anew value. What should I do so that I can use the value from the first timeslot during the second timeslot. Take note that on the second timeslot, the value changes already but what I need is the value from the previous timeslot. Am I gonna store it? How? Help please. newbie here in VHDL. Thanks.
    you need to learn basics of digital design, ie, how to code combinational and sequential logic, as well as how to connect one to the other to form an actual digital system.
    Really, I am not Sam.



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    Re: Pipeline problem VHDL

    Quote Originally Posted by ads-ee View Post
    I already showed DFF i.e. D Flip-flop. I'm not going to post the truth table, go look it up in google.
    Oh I didn't see it! Thaaanks!



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    Re: Pipeline problem VHDL

    Quote Originally Posted by nizdom View Post
    What kind of flip flop should I use? Thaanks!
    Don't instantiate individual DFF's. Just assign the value to a signal inside a clocked process. The synthesis tool will add the DFF.



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