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How to derive a Fixed Length Output signal from a variable length Input signal in ver

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H.Khan

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I have an HDL Block in which the output follows the input in such a way that when input signal is binary 0, output remains 0 but when input turns 1, output turns 1 for a preset number of clock cycles (signal_length). i.e. input may remain high for suppose 65 or 66 clock cycles but output should remain high for preset number of clock cycles. I tried to accomplish the task with Verilog. But I am having an error and I don’t know how to rectify. Hope someone can help.


Code Verilog - [expand]
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module last_ind
#(
parameter MAX_LENGTH = 262144,
parameter signal_length
)
(
   input           clk,      
   input [17:0] pkt_length,
   input           tdata,
   output          tlast
);
reg [17:0] cnt = 0;
 
always @ (posedge clk)
begin
if ((tdata==1) && (cnt<signal_length)) 
        tlast <= 1;
 else
        cnt <= 0;
 end
 assign   cnt <= cnt + 1'b1;
 endmodule

 
Last edited by a moderator:

Look what you've done in the if..else block.

Where are you driving your tlast <= 0 that will cause your o/p to go LOW?

You have made cnt <= 0 but not driving tlast to 0.
 

This piece of code looks like it should give syntax error during compile.


Code Verilog - [expand]
1
assign   cnt <= cnt + 1'b1;



assign is continuous assignment; whenever RHS changes it'll be assigned to LHS. So there's no concept of non-blocking assignment ( <= ).

If the idea is to count the clocks, cnt should be inside an always block with posedge clk in its sensitivity list.

Another thing is probably you should initialize the parameter signal_length to some default value.

It'll be a useful practice if you can visualize the circuit you want to implement before starting to code. Hardware comes first and verilog is only a tool describe that hardware.
 

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