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  1. #1
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    [Synth 8-27] complex assignment not supported

    I have a segment of vhdl code as follows:
    Code VHDL - [expand]
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    if option = '0' then
        addr1_1 := 4*addr1_2; ---4xAddress
        if s_count2 = 0 then
                block_array(block_index) <= addr1_1;
                block_index := block_index + 1;
            s_count2 <= 1;
        elsif s_count2 = 1 then
                block_array(block_index) <= addr1_1 + 1;
                block_index := block_index + 1;
            s_count2 <= 2;
        elsif s_count2 = 2 then
                block_array(block_index) <= addr1_1 + 2;
                block_index := block_index + 1;
            s_count2 <= 3;
        else
                block_array(block_index) <= addr1_1 + 3;
                block_index := block_index + 1;
            option <= '1';
            s_count2 <= 0;
            block_addr <= 0; 
        end if;
    else
        addr1_1 := 4*block_array(block_addr);
        if addr1_1 <= b1'high then
            if s_count2 = 0 then
                    block_array(block_index) <= addr1_1;
                    block_index := block_index + 1;
                db_a1 := block_addr;db_a2 := block_addr + 1;
                s_count2 <= 1;
            elsif s_count2 = 1 then
                    block_array(block_index) <= addr1_1 + 1;
                    block_index := block_index + 1;
                s_count2 <= 2;
            elsif s_count2 = 2 then
                    block_array(block_index) <= addr1_1 + 2;
                    block_index := block_index + 1;
                s_count2 <= 3;
            else
                block_array(block_index) <= addr1_1 + 3;
                block_index := block_index + 1;
                if b(block_array(block_addr)) = '1' then
                    block_array(block_addr TO 339) <= block_array(block_addr+1 TO 340);
                    block_index := block_index - 1;
                else
                    block_addr <= block_addr + 1;
                end if;
                s_count2 <= 0;
            end if;
        end if;
    end if;
    When I synthesis the code, I get the following error at line 42:
    [Synth 8-27] complex assignment not supported
    How to rectify this?

    •   Alt5th October 2017, 10:41

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  2. #2
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    Re: [Synth 8-27] complex assignment not supported

    what is "block array" ?
    But it looks like you're trying to set many values in a shift register (or is it a ram?) at once - and that is not possible in a physical ram.



    •   Alt5th October 2017, 11:09

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  3. #3
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    Re: [Synth 8-27] complex assignment not supported

    Code VHDL - [expand]
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    TYPE block_addr_array is array(0 to 340) of integer range 0 TO N*N/4-1;
    signal block_array : block_addr_array;
    SIGNAL b : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0)
    It is an array, not a RAM.
    The operation can be illustrated as follows:
    suppose: addr1_2 = 1;b(5) = '1' then
    After 4 clock cycles, block_array is like this
    [4 5 6 7]
    After 8 clock cycles...
    [4 5 6 7 16 17 18 19]
    After 12 clock cycles...
    [4 5 6 7 16 17 18 19 20 21 22 23]
    But in the 12th clock cycle, as b(5) = '1', the contents should be like this
    [4 6 7 16 17 18 19 20 21 22 23]
    To achieve this I have tried to partially shift block_array, because 4 is at the same position.



    •   Alt5th October 2017, 11:39

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  4. #4
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    Re: [Synth 8-27] complex assignment not supported

    What it is not liking is using the block_addr as the base index in the shift. Because block_addr could by any value in the array, it needs to build circuits for every possible version of block_addr.
    From this and your other post, it really feels like this is not really a hardware friendly design, and probably taking a software approach.
    Did you draw out the circuit you expect before writing any code? Did you think about pipelining the design? did you create a hardware friendly version of your compression/decompression algorithm? Did you even assess if it was hardware friendly, or if it would work better in a processor.

    This operation you show in the code is something that is more likely suited to a CPU, not hardware.



  5. #5
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    Re: [Synth 8-27] complex assignment not supported

    Code:
    block_array(block_addr TO 339) <= block_array(block_addr+1 TO 340);
    The tools don't currently understand how to do this.

    One possible way to do this would be to have the expression "x", the shifted version "x<<1", and then a mask. y = (mask&x) | ((~mask)&(x<<1)).

    This is probably still a multi-cycle operation as the logic for mask is at least equivalent to a 340 bit addition with some extra fanout. Likewise, keeping 340 integers in registers can use excessive resources depending on the value of N.



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