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Is it good to use a Pad with only one diode as ESD

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bio_man

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Hi folks,

Can I just use one type of pad for my whole padframe? all the pads are used as test points, only four of them are different which are as follows: gnd, Vinput, clock signal and Vout nodes. I have two types of pads as attached here, Pad1 has two diodes for ESD and Pad2 has only one diode. Is it ok to use Pad2 with only one diode for all Pads in the frame?

BTW, I don't have VDD terminal as it is generated on-chip using the Vinput.

- - - Updated - - -

Also, it was my intention to use Pads without protection but when I run LVS, I always encounter a problem saying that: 'The LVS job has failed to run to completion. Examine si.out and si.log in the run directory for more information'

when I checked those files nothing is given.

For the Pad1 and Pad2, LVS runs fine and the layout matches the schematic.
 

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  • Pads.png
    Pads.png
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If the "diode" is really a substrate PNP with a low avalanche
and/or snapback voltage then maybe it will do a job, but
such devices tend to concentrate a lot of pulsed power in
a small volume and need careful physical design. Do you know
the breakover I-V curve for both directions?

If one direction does not break over and stay below BVox
at the intended ESD threat-current (everybody talks voltage
but current loop is the key) then you have half-protected
the pin and the other half still fails the part.

Look to your LVS report logs, si.out and si.log may only have
netlister related info and not the LVS actual reports? Look at
the initialization window to see where LVS output info really goes.

vdd! attached to standard logic pads is normal-ish. You also
need a central vdd! - vss! clamp to complete the current loop,
else you will make the circuit core (with its plurality of weak
links) the "clamp" by default. You could attach the generated
internal vdd to vdd! global net but vinput is presumably higher
so might require its own custom protection. A fully floating ESD
+ bus ring attached to the "up" diodes' cathodes, and the central
clamp(s) (often find these distributed among multiple pads or
corner cells) can protect all pins. There ought to be a library
ESD clamp cell accompanying the rest of the pads / ESD elements.
Either a circuit based, or a single device snapback clamp, or one
that perhaps combines the two.
 
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