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[SOLVED] clearing the contents of single port RAM

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rafimiet

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I am using a RAM of size 512x512 using a word length of 18 bits. After a portion of the design flow, I have to clear its contents. Is there a way to clear it in a single clock cycle?
 

Short answer, No.

Even though you didn't even tell us which FPGA device vendor you are using, all vendors have the same restriction RAM blocks cannot be reset.
 

I am using virtex 7 and Zedboard for my design.
Originally posted by ads-ee ... Short answer, No.
We are able to initialize the RAM like this
signal mem_blobk : RAM := (others => (others => '0'));
Can we not use some similar kind of a statement to reset it?
 

See post #2
 
You would want to review the Virtex 7 handbook to understand the block RAM hardware features and why your idea doesn't work.
 

I am using virtex 7 and Zedboard for my design.

We are able to initialize the RAM like this

Can we not use some similar kind of a statement to reset it?

Initialising the contents and reset are two different things.
Initialisation takes places at power up, and is part of the chip configuration. If there were some reset mechanism, then you would need some secondary storage to store each ram's reset configuration and the logic to reset each element in a single clock cycle. So no, not possible.

You could manually reset by writing each location youself. But the question I have is why do you need to reset it? There are many ways to validate data. Why not have some address (or other logic) that marks the ram contents as valid? reset this single element and the whole ram is "reset".
 
Tricky...But the question I have is why do you need to reset it?
I have a RAM containing an image. I am compressing it to generate a bitstream. Using that bitstream, I want to regenerate the image using that bitstream. To reuse the RAM, I need to invalidate or reset its contents.
There are many ways to validate data.
But if I keep the contents there and consider them as invalid and then update them. I should be able to label the contents which are updated and which are still invalid.
Why not have some address (or other logic) that marks the ram contents as valid?
I think this will mean either all contents of the RAM are valid or invalid.
reset this single element and the whole ram is "reset".
I will like to know how this value will reset the entire RAM
 

Hi,

imagine a harddisk with FAT.
* safe a file on the harddisk: Data will be stored at a specific address on the harddisk. This file address combined with some file information is stored in the FAT - also on the harddisk.
* delete a file from harddisk: No file data will be touched /deleted. Only the FAT will be touched. It just marks the address area with the file data as available.

Klaus
 

Why are you regenerating the image back over the original image? why not just play it into some form of output buffer?
But either way, shouldnt the uncompressed image be the same size as the original?
 

why not just play it into some form of output buffer?
The frame buffer has to be of the depth 262144 and width 18 bits. I think that is not good to use an additional frame buffer of that size.
shouldnt the uncompressed image be the same size as the original?
Yes the size will remain the same.
 

That frame buffer is basically most of the ram on the chip. Why not use an external ram as a frame buffer? then you can store many frames?
But if you're overwriting the frame buffer with an image of identical size, why do you even need to reset it? it will get overwritten?
 

It is a complex thing... Actually I must reset the contents of the RAM. So I can't do it in just one clock cycle.
 

If you absolutely must reset the ram, then you have to set each address one by one.
But I propose if you need to do this, then there is a problem with your design, rather than a problem with the hardware.
 

It is a complex thing... Actually I must reset the contents of the RAM. So I can't do it in just one clock cycle.

If you need to reset the ram, you would need to double or multi-buffer. This allows you to have a RAM, or a section of a larger RAM, that is clear assuming the rate at a ram can clear is faster then the need for a newly cleared ram. For example, a BRAM36 could have a 36 bit write port and an 18b R/W port. If you need 18kb of ram you are now using 36kb of ram. The write port can clear at 36b/cycle and the r/w port can read/write at 18b/cycle. This method works best when you know you will read the entire ram.
 

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