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commit remove_clock_gates command

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r1caw ex ua6bqg

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Hi all!
I am trying to remove some ICGs from my (already placed but not cts/routed) design in ICCompiler by using command "remove_clock_gates -gating_cells $ICG_CELLNAME". Command executes correctly and at the end reports similar like this:
...Information: ICC will remove 1 clock-gating cells.
...Information: ICC will remove clock_gating for 5 registers.
...Information: Updating database...
1

But, after applying this command, $ICG_CELLNAME is not removed - I can see it on placed design (or, say, using "get_cell" command). Yes, I understand that this command reports that "ICC will remove", so the question is: how actually (physically) remove this clock gate and associated logic using command "remove_clock_gates", i.e. commit removing? I tried psynopt and place_opt commands after "remove_clock_gates" but this clock gate and associated logic already present in the design.
 

not sure if the approach you are trying is meant to work. there are other solutions, nonetheless. you can prevent that ICG cell from being there in the first place.
 

Thank you for answer! But design was already synthesized with this ICGs, so can you please provide me more information about - how prevent ICGs from placed design. Maybe I am not clearly understand you.
Actually, I need to remove this ICGs with related to clock gating logic (as I understand, using "remove_clock_gates" command will remove it and replace to simple MUX for gated registers) to prevent some timing violations on "enable" pin of ICGs.
 

First let me understand WHY you are trying to remove clock gating cells from the design. Usually you want to have as many as possible in there. Your timing violation on the pin explanation makes no sense. Tools know how to do timing paths that end on clock gates.
 

Thank you!
After place_opt stage I have some setup violations that I cannot resolve (even using psynopt) on "enable" pins of some ICGs. This violations in the clock opt-cts stage are lead to bad clock tree synthesis and huge clock skew. I dont know why ICC cannot built proper clock tree with desired skew.
So, I want ICC to remove this ICGs (power is not a big deal, because it is 10-20s ICGs) and I am trying "remove_clock_gates" command. As I told, there is no effect, and I want to know why (see the first post).
 

If you remove the cells, the paths will remain long. The setup violation will just shift elsewhere.
 

Ok, but the question is why ICC command "remove_clock_gates" cannot physically remove ICGs and associated clock gate logic? Maybe I should use smth like "commit" after this command to physically remove ICGs from design? How I can do that?
 

Additional information - when I'm applying "remove_clock_gates -gating_cell XX" first time, it will remove timing path to the XX ICG cell (but I still see this XX gate in netlist/placed design!!!), but when I run second time this command for another ICG (say, "remove_clock_gates -gating_cell YY"), it cannot remove timing path for YY ICG gate and I still see YY gate on the netlist/floorplan.
This command works also for DC Compiler with the same result, unfortunately.
Any ideas?
 

some ideas:

Have this gating_cell has freeze/dont_touch attributes?

Has the target library enough cell to remap gated flops to nongated (say, flops with enable)?
 

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