Cadence variable setup

Hi team

I have a quick question concerning variable design in cadence. I am an experienced ADS user but new to Cadence. I realized a major difference between ADS and Cadence concerning variable setup.

In ADS, the variables are built in with the circuit so if I design a localized circuit with variables (for example, a LNA, a mixer, a filter, with a few variables of the size of the transistors, cap value etc), I can just create a symbol of each of the localized cell and use it as a part of a bigger circuit directly (as for a whole receiver) and all the variables will not interfere with each other even though they have the same name.

But when I am trying to design in Cadence, the variables are built in with ADE simulation environment. Hence, when I did the same thing as I did with ADS:

1. design the localized cell of independently ( LNA, filter, mixer)

2.Incorporate the LNA etc. into the receiver. But when I launch ADE, all the variables popped up and non of them have any values.

Do I have to re-enter all the variable values?

Is there any way around it?



Thanks

Allen

AllenD said:

I have a quick question concerning variable design in cadence.

Click to expand...

Design variable's treatment is completely same between Keysight ADSsim and Cadence Spectre.

Concept of Variable's valid scope, such as local or global, is also completely same.

See both netlist.
Actually Keysight ADSsim can read Cadence Spectre's Netlist directly.

AllenD said:

and all the variables will not interfere with each other even though they have the same name.

Click to expand...

I think you mean pass parameter foir subcircuit.
Use "pPar()" skill function and edit CDF Parameters.
Surely read document of Basic of Cadence-ADE-L.

AllenD said:

1. design the localized cell of independently ( LNA, filter, mixer)
2.Incorporate the LNA etc. into the receiver. But when I launch ADE, all the variables popped up and non of them have any values.
Do I have to re-enter all the variable values?

Click to expand...

Yes.

Or save design varables to Analysis State.
Then load Analysis State.

Or Design variables can be attached to Schematics.

Anyway understand Netlist.

Hi Friend!
Thanks for your reply! I understand the pPar() function, however, I am still confused about one thing. In the example, you gave me a 3 inverter stages buffer. The design process is as follow.
1. I design the first inverter, whether or not I use pPar() function, I will have 4 variables of "lp wp ln wn". The value of these variables is restored in the ADE L state. And yes I can save/load the state to read these values.
2. I design the second and the third inverter with same fassion as the first one.
3. When I place the 3 stage inverter in the schematic, and launch ADE L, and "copy from cellview". Then all the variables will pop up with no values, right? Can you please let me know how to "Design variables can be attached to Schematics.
I really appreciate your help!
Allen
"

AllenD said:

3. When I place the 3 stage inverter in the schematic,
and launch ADE L, and "copy from cellview".
Then all the variables will pop up with no values, right?

Click to expand...

I can not understand what you want to mean at all.
Can you understand pPar() and design variable correctly ?

AllenD said:

Can you please let me know how to "Design variables can be attached to Schematics.

Click to expand...

Surely see menu of ADE-L.
However I don't recommend to attach design variables to schematics.