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problem by vivado in Rom Extraction from file !

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Hi,
I have a code for extracting a ROM from a text file. I'v used it successfully in ISE 14.7 on a spartan6. synthesize and implementation was OK.

but now I want to use it on an artix project by vivado. unfortunately vivado can not synthesize the code currently .

the code is as below:

Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;

entity My_Rom is
port(	iClk		:in std_logic;
		iAddr		:in std_logic_vector(9 downto 0);
		oData		:out std_logic_vector(15 downto 0)
	);

end My_Rom;

architecture Behavioral of My_Rom is

	type tRom is array (0 to 1023) of std_logic_vector(15 downto 0);

	impure function RomExtc (RomFileName : in string) return tRom is                                                   
		FILE RomFile     	: text is in RomFileName;                   
		variable L			: line;                                 
		variable RomData    : tRom;                                      
		variable iData    	: integer;                                      
		variable qData    	: integer;                                      
                                     
	begin  
		report "Making Mapping_Rom:";  
		-- for ii in tRom'range loop     
		for ii in 0 to 1023 loop   
			readline (RomFile, L); 		
			report "L: " & L.all;  
			iData:=0;
			read (L, iData); 
			report "iData= "&integer'image(iData);  
			RomData(ii):=conv_std_logic_vector(iData,16);
		end loop;       
		return RomData;                                                  
	end function;                                                

	constant cRom : tRom := RomExtc("Rom.coe");
	
	
	signal sAddr	:std_logic_vector(9 downto 0):=(others=>'0');
	signal sData	:std_logic_vector(15 downto 0):=(others=>'0');

begin
	
	process(iClk)
	begin
		if rising_edge(iCLk)then
			sAddr		<=iAddr;
			sData		<=cRom(conv_integer(unsigned(sAddr)));
		end if;--Clk Rising
	end process;
	-- sData		<=cRom(conv_integer(unsigned(sAddr)));
	oData	<=sData(15 downto 0);
end Behavioral;

can any body help me plz.
the version of vivado : 2015.4
 

What do you mean by "it cannot synthesise the code currently"?
What Error messages are you getting? What problems are they exactly? Does the ROM appear to be filled with incorrect values? Is thje Rom.coe file in the correct location in the project?

Please post the errors
 

Not any ROM extracted. in vivado synthesize finishes with NO Error but not any ROM is extracted as report.

By opening synthesize result netlist and viewing schematic I see no ROM extracted and all output port is connected to gnd.

I've attached ISE and vivado synthesize report.
View attachment vivado_report.txt
View attachment ISE_Report.txt
 

The report says the address port is unconnected - so no surprise it is removed.
 

can u say, why ISE has no errors and extracts a ROM? but vivado not!

Im guessing because in ISE the rom has an address connection, but in your Vivado project you didnt connect the address to anything.
So the problem is NOT in the code you posted, it is elsewhere. You need to connect the address port of the rom to something.
 

Im guessing because in ISE the rom has an address connection, but in your Vivado project you didnt connect the address to anything.
So the problem is NOT in the code you posted, it is elsewhere. You need to connect the address port of the rom to something.

this is not true, because I "set as top" in both(ISE / vivado), then there is no need to connect iAddr or iClk to anything!

I'v attached the projects of Vivado and ISE for who is interested in testing the design.

View attachment Test_Prj.rar
 

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