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    Help in encrypting or obfuscation of a design!

    Hi,

    I have a design in mixed language (VHDL,Verilog)!
    I want to deliver it to my customer to be used in Vivado.
    1) How can I encrypt or obfuscate it to be used as a black box in vivado?

    I made .dcp or .edf files that can be added to vivado, but these are netlists and can be read by anyone! by opening the dcp file I can find my design in schematics.

    2) is there any method to remove design hierarchy?(may be this one helpful for me!)

    I visited the page below about encrypting.
    3) is the Synopsys's VMC encrypted design, synthesizeable by Viavdo?
    http://www.edaboard.com/showthread.php?t=98878

    •   Alt29th September 2017, 13:30

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  2. #2
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    Re: help in encrypting or obfuscation of a design!

    A quick google got me this:
    https://www.xilinx.com/support/docum...-custom-ip.pdf

    - - - Updated - - -

    But remember, once they've compiled your design, they could look at the netlist. Though I would be surprised if anyone tried (it would probably take just as long to write their own IP)
    I doubt you can flatten the hierarchy, unless you did it yourself.

    Why are you trying to encrypt it anyway?


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    •   Alt29th September 2017, 13:59

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    Re: help in encrypting or obfuscation of a design!

    There are options to flatten hierarchy, but the names continue to reflect the original hierarchy. It might actually be more feasible to just write a script to remove all comments/formatting and modify all the signal names with random generated 20 character names.

    I wouldn't even bother trying to read a mess like that.



    •   Alt29th September 2017, 15:41

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    Re: help in encrypting or obfuscation of a design!

    Why are you trying to encrypt it anyway?
    I'm tying to block unauthorized access to my design. I have add a design that checks some conditions and if met, an OK signal is made.
    I think that if any one can read netlist, so he can find this OK signal and change it value!



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    Re: help in encrypting or obfuscation of a design!

    Quote Originally Posted by Port Map View Post
    I'm tying to block unauthorized access to my design. I have add a design that checks some conditions and if met, an OK signal is made.
    I think that if any one can read netlist, so he can find this OK signal and change it value!
    Unlikely. But why are you selling to a customer who really wants your source code? usually people buy things that they dont have the expertise to do themselves.
    To change the value of your ok signal, they would have to understand the entire code, write it out in HDL themselves, and then modify it. It probably isnt worth their time or money to do it.



    •   Alt30th September 2017, 11:40

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    Re: help in encrypting or obfuscation of a design!

    Quote Originally Posted by TrickyDicky View Post
    To change the value of your ok signal, they would have to understand the entire code, write it out in HDL themselves, and then modify it. It probably isnt worth their time or money to do it.

    Isnt it possible to modify a NGC file? perhaps in vivado by commands like write_vhdl!

    I think if one can modify a NGC file, it will not be so difficult to assign a '1' to my OK signal.



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    Re: help in encrypting or obfuscation of a design!

    Quote Originally Posted by Port Map View Post
    Isnt it possible to modify a NGC file? perhaps in vivado by commands like write_vhdl!
    I think if one can modify a NGC file, it will not be so difficult to assign a '1' to my OK signal.
    Possibly yes - but it will be a VHDL netlist. Not very easy to read or follow.
    For all practical purposes then no. And to be honest, there are not many people out there who have code anyone would really want to steal.


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