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Is it possible to have AXI 3 complete write transaction in only one clock cycle?

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Ashish Agrawal

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Hi,

Is it possible to complete one AXI 3 write transaction in just one clock cycle?
Provided This transaction has only one beat to write. And AWREADY, WREADY and BREADY are by default HIGH.
Lets say master sends the address and data in the same cycle (AWVALID, WVALID and WLAST in same cycle). Can a Slave send BRESP in the same cycle by asserting BVALID ?
Is this the protocol violation to have AWVALID and BVALID asserted in the same cycle?

Thanks,
Ashish
 

From the spec it is spelled out pretty clearly...
A3.3 Relationships between the channels
The AXI protocol requires the following relationships to be maintained:
• a write response must always follow the last write transfer in the write transaction of which it is a part
• read data must always follow the address to which the data relates
• channel handshakes must conform to the dependencies defined in Dependencies between channel handshake
signals.
Otherwise, the protocol does not define any relationship between the channels.
Click to expand...
So no the write response can't be in the same cycle as that single cycle write it follows the last write (the only write).
 

According to spec..

• a write response must always follow the last write transfer in the write transaction of which it is a part

I am confused about the "follow" word. Does it mean that BRESP can'be combo output in the same cycle of input WLAST?

I was thinking a case where slave can still follow the WLAST and generates the BRESP combinatorially in the same cycle.
 

The clock edge during the active high wlast is when the wlast is valid, therefore to "follow" that you would have to be in the next clock cycle, otherwise it would be coincident with wlast.

AXI 3 is a synchronous bus.
 

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