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testing a variable-length value

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Binome

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Hi,
I have a variable-length (depending on a generic value) word and I'd like to test whether it's null or not.
Say I have d : std_logic_vector(g_length-1 downto 0) and q : std_logic that should be '0' when d="0...0" and '1' otherwise. How could that be written?
Thanks.
 

If your tools support VHDL2008 use the VHDL reduction OR operation, otherwise you can make a function that has a for loop that uses the size of the input to iterate over the bits ORing them together.
 

Or use OR_REDUCE() function from ieee.std_logic_misc (Synopsys library).
 

Just to spell the examples above out:


Code VHDL - [expand]
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--vhdl 2008:
q <= or d;
 
-- using std_logic_misc:
q <= or_reduce(d);

 

A solution that will work with any VHDL version and no special library:


Code VHDL - [expand]
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constant d_null : std_logic_vector(g_length-1 downto 0) := (others => '0');
 
...
 
if d = d_null then
  q <= '0';
else
  q <= '1';
end if;

 

The last solution is really simple, I should have thought of it!
Thank you.
 

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