Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fingering effect on analog layout and standard cell layout

Status
Not open for further replies.
J

Jarvsiri

Newbie level 5
Joined
May 5, 2017
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
66
How the use of fingers of transistors can effect the resistance, capacitance and speed of a mosfet in analog layout and standard cell layout ?
 

Simple answer: folding a transistor will reduce S/D cap and gate resistance. However, number of S/D contacts will decrease.
 

So,do we prefer fingering/folding for analog layout or not ?
 

It all depends upon the application. Diff pairs and current mirrors require special attention. As do power devices. There are plenty of resources on the internet to help you get started
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top