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multicycle path between two flops latched by two different clocks

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slakshmi

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Can someone help me on how to specify a multicycle path from FF1/CK to FF2/D
FF1 clocked by CLK1 and FF2 clocked by CLK2

I tried this, but the tool complains that -clock_from and -clock_to are obselete, and gives an ERROR and ignores that constraint

set_multicycle_path -clock_from [get_clocks CLK1] -from [get_pins FF!/CK] -clock_to [get_clocks CLK2] -to [get_pins FF1/D]

Thanks
 

A multicycle path is a path that is not required to be stable within a 1 clock cycle period. It allows for relaxation of the timing constraints for things like logic that is enabled every other clock cycle. It is done on a path where the source and destination clocks are the same clock.

A multicycle path is not used to constrain asynchronous clock domains, which is what you seem to be doing.
 

slakshmi said:
Can someone help me on how to specify a multicycle path from FF1/CK to FF2/D
FF1 clocked by CLK1 and FF2 clocked by CLK2

I tried this, but the tool complains that -clock_from and -clock_to are obselete, and gives an ERROR and ignores that constraint

set_multicycle_path -clock_from [get_clocks CLK1] -from [get_pins FF!/CK] -clock_to [get_clocks CLK2] -to [get_pins FF1/D]

Thanks
Click to expand...

the -from -to options are meant to be used on flip flop pins, not on clock objects.
 

set_multicycle_path 5 -from [get_clocks CK] -to [get_clocks CLK2] -start -setup
set_multicycle_path 4 -from [get_clocks CK] -to [get_clocks CLK2] -hold

This will set multicycle path between two clocks
 

There is no sense to define a multicycle path between two clock domains.
Or you should mention us the clocks are related with divider ratio.

FF on CLK1 and FF on CLK2, if CLK1 & CLK2 are asynchronous should be declare as false path between them not a multicycle path.
 

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