Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

RF Loss from Bottom Plate of MIM Capacitor

Status
Not open for further replies.
pancho_hideboo

pancho_hideboo

Advanced Member level 5
Joined
Oct 21, 2006
Messages
2,847
Helped
767
Reputation
1,536
Reaction score
733
Trophy points
1,393
Location
Real Homeless
Activity points
17,490
We can not ignore RF Loss from Bottom Plate of MIM Capacitor to substrate of Silicon(Psub).

I would like to reduce this loss.
My application of MIM is RF DC block Capacitor for input of 900MHz RFID Rectifier.

See attached figure where I show four structures.

RF signal is inputed to Top Plate and Bottom Plate is connected to Rectifier input.

Which is better regaring RF Loss from Bottom Plate ?
 

Attachments

  • 170923-203911.png
    170923-203911.png
    78.1 KB · Views: 374

Laying down a layer just underneath of the bottom palte of the MIM will slighthly ( maybe more) shift the cap. value due to MIM-Layer-GND Relationship.
A Polysilicon layer may be layed down but I'm not so sure..
 

BigBoss said:
Laying down a layer just underneath of the bottom palte of the MIM will slighthly ( maybe more) shift the cap. value due to MIM-Layer-GND Relationship.
Click to expand...
Right.
However it is very very small.
For example, an increase is around 10~20fF for C=1.8pF.
 

pancho_hideboo said:
We can not ignore RF Loss from Bottom Plate of MIM Capacitor to substrate of Silicon(Psub).
Click to expand...

Yes, an accurate MIM model should be used. The substrate coupling from MIM bottom can be modelled with Cox + Csub||Rsub, similar to spiral inductors. We've published a MIM modelling paper recently:
https://ieeexplore.ieee.org/document/7839730/

You cannot avoid capacitance to the substrate. Your floating shield has no effect, the grounded shield increases shunt C. The best option is to create a defined environment, so that you get predictable shunt path that you can model properly. That's the approach in the paper linked above, similar to your case (3).
 
Last edited:

volker@muehlhaus said:
That general statement is not true
Click to expand...
No.
This is true as far as narrow band application where reactive matching is used.

Back to MIM, our TEG result shows loss is small for (3) than (4).
(3) require large area, that is a reason why I prepare (4).

However I have not confirmed (1) and (2).

These structures are all provided as PDK of famous foundary.
However simulation using models which are provided from foundary show only negligible difference between these four structures.

I think models are not good, so I can not judge from simulation.
 
Last edited:

Yes, correct for the grounded shield, if you can absorb the increase in shunt C into the circuit, then this is an option!
However, the floating shield is useless, as it is parallel to the E field lines and has no effect at all.
 

Of course you drive the bottom plate and take signal
off the top plate, right?

Beyond that what about co-driving the guard with a
separate, maybe smaller, amp branch? Or maybe just
a second match network off the primary amp?

I have seen in some RF CMOS flows, multiple MIM
options (one at lower levels, one using the top 2) and
obviously the "higher" would be better for substrate
losses.

Making underlying silicon have the highest possible
resistivity can cut the loss (effectively adding a series-R
zero). Like whatever sits under a "native" FET. But this
may be otherwise set, in the library PCell?
 

dick_freebird said:
Of course you drive the bottom plate and take signal
off the top plate, right?
Click to expand...
If we care noise coupling from substrate, bottom plate sampling scheme is effective.
Howerve, no effect for RF loss reduction

dick_freebird said:
Making underlying silicon have the highest possible
resistivity can cut the loss (effectively adding a series-R
zero).
Click to expand...
Lower resitivity is also effective.
 

Attachments

  • 170924-023759.png
    170924-023759.png
    15.3 KB · Views: 99
  • MIM2.png
    MIM2.png
    38.4 KB · Views: 96
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top