enable vs reset in digital IC

Hello everybody,
I'm a little bit confused about the difference of reset and enable in digital IC...
for a design point of view, the enable signal helps to prevent glitches at the output port, so by enabling the circuit only when the data inputs are ready the output hasn't got any of it.
the reset signal instead initialize every registers, fsm etc to its start point.
am i right? if yes, i'm thinking that for a simple fsm, are both the signals present?
if yes what's the meaning of enable in a single fsm? a moore fsm reacts only at every clock edge so enable isn't very meaningfull; or i'm just missing some concept that i'm not so good to find by googling.
Thank you so much

Hi,

I think this question can not be answered generally.
Both signals are not mandatory in digital circuits.

Please refer to dedicated devices (datasheets).
Usually you will find the function of both signals in it's datasheet.

Klaus

There are the two different functions in a counter IC:

(a) ENABLE (or disable) count

(b) RESET count to zero

- - - Updated - - -

And you can activate either function regardless what the other is doing.

Thank you for your replies.
It's straightforward for a counter, and i can not refear to any datasheet because i'm implementing a fsm in vhdl so i'd like to know the differences between the two signals in order to implement the correct one. For sure reset is mandatory, but what about enable? Could be usefull for the layout of the ic?

Enable/disable may save some switching power. Especially, when the enable converted to clock-gating during synthesis.

Hi,

If you design it on your own: Generate those signals that you need for your function. You even may name them as you like.

But for a FSM:
* RESET: should should place your FSM to an initial state. Often the same state as after power_on.
* ENABLE: usually it is clocked by a continous running high frequency clock. and stepping to the next state may be caused by the edge of an additional input. Preventing to enter the next step can be made with an ENABLE/DISABLE signal.

Klaus

carmeloA said:

Thank you for your replies.
It's straightforward for a counter, and i can not refear to any datasheet because i'm implementing a fsm in vhdl so i'd like to know the differences between the two signals in order to implement the correct one. For sure reset is mandatory, but what about enable? Could be usefull for the layout of the ic?

Click to expand...

It has very little to do with layout. You add an enable signal if your logic needs one. That simple.

This is somewhat of a generalization, as it can depend on the implementation/design.

Usually a reset is used to clear/reset the state/memory of the system to a predetermined value. Can be isolated or global.

Whereas an enable usually allows the system to suspend operation such that it maintains memory but does not respond to input internally (state/memory) or externally (output). (Ex. Gated latch) Enables signals can also allow internal states to change, while externally those changes are not visible. (Ex. Output Enable)

Reset and Enable are related and despite what some people have said they are both required.

Reset is used to put the circuit into a known good start state. Some circuits like clock dividers have to run during the power on reset time and they must be designed to self start and run from any possible initial state. They are not reset by the power on reset signal but they must still have a reset so that they can be reset for simulations and test. All logic must have reset. If it is not on the power on reset domain then your verification plan must cover how you are going to prove that it will work from ANY initial state (Hint: That can be really hard to do).

Enable can be used in two different ways. In the old days we would connect everything to a continuously running clock and clock on every rising edge. Then power became a concern so now we provide a Enable signal so that we only clock every X number of clocks. It saves power and lets us synthesize for multicycle clocks. So do you need to provide an Enable signal? The answer is YES. You are only the component designer. The decision to use a clock enable is made by the clock system designers and the test engineers. You do not get to do their job. Put in an Enable and if they don't need it then they will tie it off to an active state.


The other way to use Enable is as a functional enable. You design an ethernet interface with an Enable bit in the command status register set. This bit powers up disabled while you write setup values into all the other registers. Once done you set this bit to start the component and clear it to stop.

The difference between the two Enables is that for a clock enable you hold the current state when disabled and for the functional Enable you return the flop to its reset state when disabled. A functional enable is the same as a synchronous reset.


Every flip flop must have both a clock Enable that holds the current state and a synchronous reset that also can serve as a functional enable. Let the end user tie them off if they don't need them.

Do not make the mistake of giving the Reset priority over the Enable signal. When Reset occurs you must wait until the next Enable time to change the flop or you will have a big problem with timing.

John Eaton

RESET pin is used to reset flip-flops in gate-level-netlist otherwise flip-flop goes in undefined state in ASIC ICs .
ENABLE is used to select chip, it is generally used by proper addressing of address buses to select IC.

sanjaysharmaiitk said:

RESET pin is used to reset flip-flops in gate-level-netlist otherwise flip-flop goes in undefined state in ASIC ICs .
ENABLE is used to select chip, it is generally used by proper addressing of address buses to select IC.

Click to expand...

this is misleading. reset is a reset, enable is an enable. both will be present in pretty much all code that you write.

it has nothing to do with whether you are doing gate level simulation or building asics or 'selecting chip'.

ThisIsNotSam said:

this is misleading. reset is a reset, enable is an enable. both will be present in pretty much all code that you write.

it has nothing to do with whether you are doing gate level simulation or building asics or 'selecting chip'.

Click to expand...

it is not for all designs.
i do not like to misleading anyone.
i have share my own experience concerned with ASIC IC design.
I have designed a small design of UART in that initially i had not used RESET pin then in post synthesis simulation problem came as all outputs were stuck at undefined state.
after using RESET it started work.

sanjaysharmaiitk said:

it is not for all designs.
i do not like to misleading anyone.
i have share my own experience concerned with ASIC IC design.
I have designed a small design of UART in that initially i had not used RESET pin then in post synthesis simulation problem came as all outputs were stuck at undefined state.
after using RESET it started work.

Click to expand...

essentially you are saying that you have used a reset signal to fix the most naive of mistakes ever: forgetting to reset the circuit. I am sorry, but like I said, this has nothing to do with anything. Resets and enables are added because they are needed, not to make your naive testbench pass. sigh.

Hi,

I have designed a small design of UART in that initially i had not used RESET pin then in post synthesis simulation problem came as all outputs were stuck at undefined state.

Click to expand...

I wonder how a UART comes into an undefined state.
It is a state machine. Either it is in idle state, or - if triggered - it will run 10 bit clock cycles (without a conditional stop/delay) and then automatically enters the idle sate.
So if it hang´s ... I assume there is a programming error. So the RESET just cures the symptom, but not the cause.

Klaus

KlausST, you missed the OPs real issue, the design FFs were at an undefined state. Probably all X's in a gate level simulation. Without a reset in the design their design did not simulate correctly in either behavioral simulation of the HDL (which they likely did not do) or as a gate level simulation.

Typical novice problem, jumping straight from coding directly to gate level simulation or in the case of FPGA directly to the hardware.

Hi,

isn´t there a defined state after power up for a real circuit?
Or is this only a simulation problem?

Klaus

KlausST said:

Hi,

isn´t there a defined state after power up for a real circuit?
Or is this only a simulation problem?

Klaus

Click to expand...

Not for an ASIC or at least for the FF library cells I used back 10 years ago.
SRAM based FPGAs though have the FF power up values in their bitstreams. I'm not sure if flash based FPGA FFs are guaranteed to power up to a particular value. Haven't looked, nor do I rely on the default power up state for any FPGA/ASIC/PLD/CPLD/etc FF.

Hi,

didn't know this about ASIC.

Klaus