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Is that considered a combinatorial loop and how bad is it ?

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joul

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Let's say we have

Code:
entity ent  is
  port (
  ...
  ...
  a : out std_logic
   );
end ent;

architecture archi of ent is
  signal s1,s2 : std_logic;
begin
  ...
  s2 <= <some condition>;
  ...
  [B]s1[/B] <= '1' when s2 = '0' [B]or s1 = '1'[/B] else '0';
  a <= s1;
end archi ;

Basically I want a to go to '1' if s2 is '0' and stay that way when s2 goes back to '1'.

Let's say there is no clock available.

It works as expected on a FPGA but is that considered a combinatorial loop and is it bad practice ?

Thanks
 

It would only be a comb loop if S2 also was dependent on a, so as long as that's not the case, then no problem.
 
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    FvM

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It would only be a comb loop if S2 also was dependent on a, so as long as that's not the case, then no problem.

Thanks for your answer.

So the fact that s1 is part of the condition in its own assignment is not a problem ?
 

Code:
s1 <= '1' when s2 = '0' or s1 = '1' else '0';
O.K., that is in fact a combinational loop. But it makes no sense because s1 is never reset.

That's the point, it should never go back to '0' once it goes to '1'. Is this logic safe or not ?
 

Code:
s1 <= '1' when s2 = '0' or s1 = '1' else '0';
O.K., that is in fact a combinational loop. But it makes no sense because s1 is never reset.

- - - Updated - - -

There must be at least a power-on reset. Apart from this point it's safe. You have to assure that s2 or the preceding logic can't generate glitches.
 
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    joul

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There must be at least a power-on reset. Apart from this point it's safe. You have to assure that s2 or the preceding logic can't generate glitches.

To clarify, s2 is set on power on, so everything should be fine right ?
 

Yes, but the only way to reset it is power cycle the device.
Must admit missed the S1 reference to itself. The first time
 

First point is that you need to enforce a low power-on state of s1, otherwise the logic could be optimized to "nothíng" by the synthesis tool.

I would prefer a dedicated reset input though.
 

Let's say we have

Let's say there is no clock available.

... is it bad practice ?

You need to explain why you do not have any clocks in this design. This sounds like weird academics doing thing with no understanding of FPGAs -- who would also resent that statement because they have PHDs and thus could understand anything even though they intentionally wont.
 

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