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How to Declare a 3D array as an input inside the port

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Yogeshwaran

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Hi,
I need to declare a 3D array as an input inside the entity.

I created a library like this

type my_2d_array : is array ( 0 to m ) of std_logic_vector(0 to k) ;
type my_3d_array : is array ( 0 to n ) of my_2d_array ;

I used my_3d_array as my data type and compile done perfectly. But when I tapping my actual input to this entity input it was not catching the real value.

I am not sure where is the problem. Can someone help me??
 

Your question is not clear. What does "not catching the value" mean?

Why not post the real code and specify what the real problem is?
 

@ TrickyDicky
Actually I'm doing formal verification for a encoding unit. This encoding unit has a 3D signal which stores the encoded data. For me, That signal is an input So I need to declare this signal inside the port as an input. Hence I created a package for this specific data type. Here is my actual code:

PACKAGE 3d_data_pkg is
type my_2d_array : is array ( 0 to 16 ) of std_logic_vector(0 to 7) ;
type my_3d_array : is array ( 0 to 16 ) of my_2d_array ;
END 3d_data_pkg;

entity local_driver is(
Encoded_data : IN my_3d_array
);
end entity;

Like I said no issues with compile but That design signal data is not written in this 3d data array. This is my Problem.
 

I just see an empty entity with 3d input. How do you drive the input port, how do you read it?
 

Are you actaully doing Formal Verification (with a tool like Jasper Gold or Questa Formal)? Your verification space is going to get rather large with 3d arrays. or just standard dynamic verfication? Or is this just a testbench you're trying to run?

I still dont understand the problem. If it's not "catching the value", I suggest you connected it incorrectly.
 

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