promach
Advanced Member level 4
The following gave me register array. Why ?
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 `include "define.v" module memory_block (clk, write_enable, waddr, raddr, data_write, data_read); input clk, write_enable; input [(`ADDR_WIDTH-1) : 0] waddr; input [(`ADDR_WIDTH-1) : 0] raddr; input [(`DATA_WIDTH-1) : 0] data_write; // data to be written into memory output reg [(`DATA_WIDTH-1) : 0] data_read; // data read out from memory reg [(`DATA_WIDTH-1) : 0] memory [(`MEMORY_SIZE-1) : 0]; always @(posedge clk) begin data_read <= memory[raddr]; if (write_enable) memory[waddr] <= data_write; end endmodule