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Logic scope coding approach

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The following gave me register array. Why ?

Code Verilog - [expand]
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`include "define.v"
 
module memory_block (clk, write_enable, waddr, raddr, data_write, data_read);
 
input clk, write_enable;
input [(`ADDR_WIDTH-1) : 0] waddr;
input [(`ADDR_WIDTH-1) : 0] raddr;
input [(`DATA_WIDTH-1) : 0] data_write;  // data to be written into memory
output reg [(`DATA_WIDTH-1) : 0] data_read;  // data read out from memory
 
reg [(`DATA_WIDTH-1) : 0] memory [(`MEMORY_SIZE-1) : 0];
 
always @(posedge clk)
begin
     data_read <= memory[raddr];
     
    if (write_enable)   
        memory[waddr] <= data_write;
end
 
endmodule
 

The tools can choose the implementation. When MEMORY_SIZE is low it might be possible that other resources are less optimal. If the device doesn't have distributed RAM for example, it would not be efficient to use a block ram for a small number of elements.

The tools can also be very restrictive on coding style. Perhaps the second index needs to be [0 : MEMORY_SIZE-1].
 
vGoodtimes said:
The tools can choose the implementation. When MEMORY_SIZE is low it might be possible that other resources are less optimal. If the device doesn't have distributed RAM for example, it would not be efficient to use a block ram for a small number of elements.
Click to expand...

Thanks. Larger MEMORY_SIZE helps to infer RAM.

Screenshot from 2017-09-21 11-02-24.png
 

Use a RAM_STYLE attribute on the memory array to force block RAM usage.
 

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