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need some help to design digital circuit

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Adnan86

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Hi, I want to design a circuit that :
input is pulse with different width, but i just want to have first pulse in output. do you have any idea to design this with gate level.
I will appreciate if someone help.
thanks
 

Hi, I want to design a circuit that :
input is pulse with different width, but i just want to have first pulse in output. do you have any idea to design this with gate level.
I will appreciate if someone help.
thanks

this is not very digital, so the implementation would need to do some sort of high speed clock sampling and counting to figure out the pulse length
 
so, what can I do, for detect of first pulse of my input ??
 

You want a multiplexer that outputs the first pulse?
 
HOW ?
Multiplexer cant detect which pulse of my input its a first .
 

Hi,

Your description is not very good, it takes time to find out what you mean.
No voltage, no frequency, no timing, ni diagram....

So maybe a flipflop that is set with the falling edge of the pulse.
Inver this output and feed it to an AND gate.
Second input of the AND gate is your input pulse.
Output of the AND gate is the output pulse.

You don't say if it is ever being activated again...

Klaus
 
I write this idea for my purpose with verilog code


Code:
module pulseD(
	input	data_in, rst,
	output reg data_out);
	
	reg [3:0] count;
	reg	temp_in;
	always @(*)
	begin
		temp_in <= data_in;
		if (rst) begin
			count <= 0;
		end
		else if (temp_in != data_in) begin
		count <= count + 1;
		end
	end
	
	always @(*)
	begin
		if (count <= 2'b10) begin
		data_out <= data_in;
		end
		else
		data_out <= 0;
	end
But I want to design it with gates, Sorry for my poor writing, I wish you understand

- - - Updated - - -

pulse.png
something like that. this picture is my output simulation of verilog code
 

You code doesn't make a whole lot of sense, for instance the code:

Code Verilog - [expand]
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always @(*)
begin
  temp_in <= data_in;
end


results in a wire, so you are comparing a wire to a wire which is always going to compare the same so is utterly meaningless in terms of hardware.

Building counters in combinational circuits is not going to work either.
 
You code doesn't make a whole lot of sense, for instance the code:

Code Verilog - [expand]
1
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4
always @(*)
begin
  temp_in <= data_in;
end


results in a wire, so you are comparing a wire to a wire which is always going to compare the same so is utterly meaningless in terms of hardware.

Building counters in combinational circuits is not going to work either.

So, if this cant work. what is your advice for me, I want to design a simple gate level circuit that work like this simulation :pulse.png
It means in output I need just first pulse of my signal.
 

So, if this cant work. what is your advice for me, I want to design a simple gate level circuit that work like this simulation :View attachment 141260
It means in output I need just first pulse of my signal.

nothing makes sense here. you DO NOT want to design gate level, you want to design at RTL level and synthesize to gates. just google a template for synchronous counter in verilog and take it from there.
 

Hi,

what is a counter good for this problem?

Klaus
 

Hi,

what is a counter good for this problem?

Klaus

just for determine number of level changer, So I can use it, whenevre 2 times input level changed, output = input after that output = 0.
So with this idea output show just first pulse of input.
 

You can try a simple solution like below. It blocks data_out after the first falling edge of data_in.

Code Verilog - [expand]
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module pulseD(
  input data_in, rst,
  output reg data_out);
    
  reg pulse_on;
 
  always @(posedge rst or negedge data_in)
    begin
      if (rst)
        pulse_on <= 1;
      else
        pulse_on <= 0;
    end
  assign data_out = data_in & pulse_on;

 

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