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Calculating capacitance from frequency response

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Vijay Vinay

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Hello all,
I have come up with a new doubt, this time. I need to calculate the parasitic capacitance for the inputs of my circuit design. I am working in Cadence Virtuoso 6.1 currently and I need guidance regarding the calculation of the parastic capacitance using frequency response (Manually). Previously, I used the Parasitics option within the Plugins option in Cadence Virtuoso 6.1 for calculating the parasitic capacitance. However, now I need to cross check these results using the frequency response curve. I have used a simple technique of sweeping a Vdc supply from 100mV to 2V and measured the input current for my circuit (based on the formula C= I/ (dV/dT)). I got some results which aren't the same as the results I got while using the Parasitics option (~4fF difference). I don't know whether what I have done is correct or not. I have uploaded the pictures of my design here. Right now what I need is, I need to use another method of frequency respone for calculating the capacitance, which I don't know. Could anyone help me to work on this.

circ_test.jpeg

test.jpeg

I_vs_Vin.jpeg

FYI, I have used a Vdc supply for sweeping the Vin. I have measured Iin , and calculated Capacitance using C= I/(dV/dT)), C= 28.42fF (I have a question, if this capacitance is Ouput capacitance or Input capacitance. Please answer this question, if you know?)

These are the calculated parasitic capacitances for this circuit using the Parasitics Plugin option within Virtuoso 0.6.1

par_cap.jpeg
 

1. If you are applying a linear (in time) voltage ramp, the current should be constant over time - why is it varying over voltage (time) in your case?

2. What is that element X0?

3. Parasitic prober show you only parasitic capacitance of nets.
When you do circuit simulation, you will see the impact of device related capacitances - such as capacitance of the body of resistor R0, and element X0, that's why measured / simulated capacitance may be larger than the parasitic capacitance of the net.

4. In my opinion, the best way to simulate capacitance, is to apply a small-signal AC voltage top the input port, and measure current. Imaginary part of the current is i*omega*C*Vac.
 
The best that can be done, if I have understood your problem, is to have an estimate of the equivalent capacitance of the setup at some given frequency. But you need a model consistent with the load curve. You have basically three parameters voltage, current and frequency that are interrelated in a graphical form. You can determine the equivalent capacitance at some point of your interest.
 

Since the input voltage is linearly swept why the current is not linear ?? If the parasitic element is constant, the current should also be constant.
I think there is a discrepancy in simulation idea.
 
1. If you are applying a linear (in time) voltage ramp, the current should be constant over time - why is it varying over voltage (time) in your case?

2. What is that element X0?

3. Parasitic prober show you only parasitic capacitance of nets.
When you do circuit simulation, you will see the impact of device related capacitances - such as capacitance of the body of resistor R0, and element X0, that's why measured / simulated capacitance may be larger than the parasitic capacitance of the net.

4. In my opinion, the best way to simulate capacitance, is to apply a small-signal AC voltage top the input port, and measure current. Imaginary part of the current is i*omega*C*Vac.

2. X0 element is a rpad which is used for removing the parasitic capacitances, short circuit spikes and unwanted currents within the circuit design.

3. Ah ok, I got it. How to subtract the capacitance of the resistor R0 from the total parasitic capacitance that is calculated

Thanks for your info timof
 

If R0 is used just to break the net into to, for LVS purposes - then make it very short (small L value), then its capacitance will be very small and can be safely ignored.
Otherwise, its body capacitance will be assigned to its pins, and probably mixed with capacitance caused by M6 wiring - so untangling them may be impossible at all.

One more thing - in circuit simulation, the net on the other side of R0 will also contribute to simulated/measured capacitance at node IN, but in parasitic extraction, it will be assigned to a different net (VOUT)?
 
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