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    Timing simulations in vivado

    I get the following timing report after implementing design for 10ns clock period
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    Does it simply mean that I have to increase the clock period? Or it means I have to make some input/output delay adjustments? I want to know what it means and how to rectify?

    •   Alt14th September 2017, 13:58

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    Re: Timing simulations in vivado

    It means 69 paths did not make the 10 ns period the worst one was missing by 462 ps. i,e. 10.462 ns.

    Depending on the issue it may be easy or hard to resolve the timing violation.



    •   Alt14th September 2017, 14:05

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    Re: Timing simulations in vivado

    With such a small failure, you may get it to work simply by changing the seed.
    But it may be worth investigating the cause of the failure (it could be that this is a good seed, and a new seed simply makes it worse).



    •   Alt14th September 2017, 14:19

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    Re: Timing simulations in vivado

    Is there any relation between worst pulse width slack and clock period? I mean is period = 2*WPWS? Also I want your recommendations about the approach to fix the error for minimum possible clock period? Also how can we find the maximum frequency for the design in vivado? In ISE, it was easily available with the timing report.



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    Re: Timing simulations in vivado

    The easiest way to fix the error is the modify the source code to increase pipelining. This will give the best increase in max frequency.
    But you should already have a target frequency in mind, based on the throughput you require, or limitations from existing interfaces.



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