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  1. #1
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    BGR circuit stb analysis

    Hi all,

    I am trying to do stability analysis for BGR (bandgap reference) circuit using iprobe in cadence virtuoso.
    I am breaking the loop between opamp's output and gate of two PMOS transistors (as shown in attached fig).
    when I am plotting loop gain and loop phase what I see is, loop phase is starting from 0 deg and then reaching to 90 deg (results are attached here). I have a doubt that generally loop phase should start from 180 deg to ensure negative feedback. I have attached the block diagram to explain how I am braking the loop and loop gain and phase results are also attached. When I see phase margin for this system I am getting around 85.3 deg.

    Can somebody suggest why phase is starting from 0 deg not 180 deg ? Is this the correct method to do stb analysis for BGR? Any help will be appreciated.

    Thanks in advance.

    https://obrazki.elektroda.pl/9877215700_1505307702.png
    https://obrazki.elektroda.pl/9272783800_1505307835.jpg
    https://obrazki.elektroda.pl/4056930100_1505307846.jpg
    https://obrazki.elektroda.pl/6579105700_1505307857.jpg

    •   Alt13th September 2017, 14:14

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  2. #2
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    Re: BGR circuit stb analysis

    In this BGR circuit, You should determine where is the negative feedback loop, and then break the loop with iprobe. The position of breaking at the output of opamp is wrong, I think.

    BRs



    •   Alt15th September 2017, 14:35

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  3. #3
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    Re: BGR circuit stb analysis

    Quote Originally Posted by vieha007Electronic View Post
    In this BGR circuit, You should determine where is the negative feedback loop, and then break the loop with iprobe. The position of breaking at the output of opamp is wrong, I think.

    BRs
    I think we need to take care of both the feedbacks, that is why I am breaking the loop from a common point and checking weather the total feedback is negative or not.



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