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    "ERROR: [Common 17-165] Too many positional options when parsing

    I try to simulate a design with the test bench as follows:
    Code VHDL - [expand]
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    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE std.textio.all;
     
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    USE ieee.numeric_std.ALL;
     
    ENTITY fsm_tbw IS
    END fsm_tbw;
     
    ARCHITECTURE behavior OF fsm_tbw IS 
     
        -- Component Declaration for the Unit Under Test (UUT)
     
        COMPONENT FSM_all
        PORT(
             rst : IN  std_logic;
             clk : IN  std_logic;
             i : IN  std_logic_vector(7 downto 0);
                out_en : OUT std_logic;
             y : OUT  std_logic_vector(10 downto 0)
            );
        END COMPONENT;
        
     
       --Inputs
       signal rst,out_en : std_logic := '0';
       signal clk,endoffile : std_logic := '0';
       signal i : std_logic_vector(7 downto 0) := (others => '0');
     
        --Outputs
       signal y : std_logic_vector(10 downto 0);
     
       -- Clock period definitions
       constant clk_period : time := 10 ns;
        
        -- TEXT FILE --
        FILE g: TEXT OPEN WRITE_MODE IS "trans.txt";
        FILE f: TEXT OPEN READ_MODE IS "orig.txt";
     
     
    BEGIN
     mapping: FSM_all port map (rst, clk,i,out_en,y);
       -- Clock process definitions
    rst <= '0';
    clk <= NOT clk AFTER 10ns;
     
     
       -- Stimulus process
       reading: process
            VARIABLE l: LINE;
            VARIABLE good_value : BOOLEAN;
            VARIABLE pixl1 : INTEGER RANGE 0 TO 255;
       begin    
            wait until clk = '1' and clk'event;
            if (not endfile(f)) then
                READLINE(f,l);
                READ(l,pixl1,good_value);
                i <= std_logic_vector(to_signed(pixl1,8));
            else
                endoffile <='1';         --set signal to tell end of file read file is reached.
            end if;
        end process reading;
        writing: process
            VARIABLE m: LINE;
            VARIABLE good_value : BOOLEAN;
            VARIABLE pixl3 : INTEGER RANGE 0 TO 255;
            variable count : INTEGER RANGE 0 TO 255;
       begin    
            wait until clk = '1' and clk'event;
            if out_en = '1' then
                if count <= 262144 then
                    pixl3 := to_integer(signed(y));
                    WRITE(m,pixl3);
                    WRITELINE(g,m);         --set signal to tell end of file read file is reached.
                    count := count + 1;
                end if;
            end if;
        end process writing;
        
     
    END behavior;
    I get the following errors:
    launch_simulation
    INFO: [USF-XSim-27] Simulation object is 'sim_1'
    INFO: [USF-XSim-37] Inspecting design source files for 'fsm_tbw' in fileset 'sim_1'...
    INFO: [USF-XSim-97] Finding global include files...
    INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
    INFO: [USF-XSim-2] XSim::Compile design
    INFO: [USF-XSim-61] Executing 'COMPILE' step in 'D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.sim/sim_1/behav'
    "xvhdl -m64 --relax -prj fsm_tbw_vhdl.prj"
    INFO: [VRFC 10-163] Analyzing VHDL file "D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sources_1/new/FSM_all.vhd" into library xil_defaultlib
    INFO: [VRFC 10-307] analyzing entity FSM_all
    INFO: [VRFC 10-163] Analyzing VHDL file "D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sim_1/new/fsm_tbw.vhd" into library xil_defaultlib
    INFO: [VRFC 10-307] analyzing entity fsm_tbw
    INFO: [USF-XSim-3] XSim::Elaborate design
    INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.sim/sim_1/behav'
    Vivado Simulator 2015.4
    Copyright 1986-1999, 2001-2015 Xilinx, Inc. All Rights Reserved.
    Running: C:/Xilinx/Vivado/2015.4/bin/unwrapped/win64.o/xelab.exe -wto b83cae4e17f842aa960b1ce68e23e5d4 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot fsm_tbw_behav xil_defaultlib.fsm_tbw -log elaborate.log
    Using 2 slave threads.
    Starting static elaboration
    Completed static elaboration
    Starting simulation data flow analysis
    Completed simulation data flow analysis
    Time Resolution for simulation is 1ps
    Compiling package std.standard
    Compiling package ieee.std_logic_1164
    Compiling package std.textio
    Compiling package ieee.numeric_std
    Compiling architecture behavioral of entity xil_defaultlib.FSM_all [\FSM_all(3,256,8,16,11)\]
    Compiling architecture behavior of entity xil_defaultlib.fsm_tbw
    Built simulation snapshot fsm_tbw_behav

    ****** Webtalk v2015.4 (64-bit)
    **** SW Build 1412921 on Wed Nov 18 09:43:45 MST 2015
    **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

    source D:/Local -notrace
    invalid command name "Common"
    while executing
    "Common 17-165"
    invoked from within
    "ERROR: [Common 17-165] Too many positional options when parsing 'projects/vivado_learning_project/vivado_learning_project.hw/webtalk/labtool_webtalk.l..."
    (file "D:/Local" line 1)

    INFO: [Common 17-206] Exiting Webtalk at Wed Sep 13 12:11:12 2017...
    INFO: [USF-XSim-4] XSim::Simulate design
    INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.sim/sim_1/behav'
    INFO: [USF-XSim-98] *** Running xsim
    with args "fsm_tbw_behav -key {Behavioral:sim_1:Functional:fsm_tbw} -tclbatch {fsm_tbw.tcl} -log {simulate.log}"
    INFO: [USF-XSim-8] Loading simulator feature
    Vivado Simulator 2015.4
    ERROR: File orig.txt could not be opened
    on HDL file D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sim_1/new/fsm_tbw.vhd line 67
    ERROR: [Simtcl 6-50] Simulation engine failed to start: The Simulation shut down unexpectedly during initialization.

    Please see the Tcl Console or the Messages for details.

    ERROR: [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information.
    launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 754.379 ; gain = 35.941
    The same testbench works fine in ISIM (used in ISE 14.4). Can anybody tell me what to do?

    •   Alt13th September 2017, 07:55

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  2. #2
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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    ERROR: File orig.txt could not be opened
    on HDL file D:/Local Disk/PHD_WORK/xilinx_projects/vivado_learning_project/vivado_learning_project.srcs/sim_1/new/fsm_tbw.vhd line 67
    Are you sure Vivado can access that file?


    I do something like...
    Code:
    use ieee.std_logic_textio.all;
    use STD.textio.all;
    .
    .
            file rx_data : text ;         -- Declare read file variable 
    .
    .
    .
    
            -- Open file for reading              
            file_open(rx_data, "C:\Work\elog\fpga_a7\sources\sim\ddd_elog2host_data.txt", read_mode);
    .....yes, I do this for fun!



  3. #3
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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    "ERROR: [Common 17-165] Too many positional options when parsing 'projects/vivado_learning_project/vivado_learning_project.hw/webtalk/labtool_webtalk.l..."
    (file "D:/Local" line 1)
    This error comes when you are instatiating a component using positional association and are trying to connect more things than exist in the component (please use named association to avoid this).

    The other indicates vivado cannot open orig.txt



    •   Alt13th September 2017, 09:32

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  4. #4
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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    Tricky...please use named association to avoid this
    Can you please elaborate on this wrt above code?



  5. #5
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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    The path it points to is obscured. So I dont the problem is in the testbench

    as for named association:

    Code VHDL - [expand]
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    mapping: FSM_all port map (
      rst => rst, 
      clk => clk,
      i => i,
      out_en => out_en,
      y => y);



  6. #6
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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    It looks to me like all the errors are mostly caused by running in a directory with a space in the name.
    D:/Local<space>Disk/PHD_WORK/

    That space in the name is breaking the auto generated scripts created when running a simulation from the Vivado GUI. This kind of stuff is why I only use the GUI to generate a script to find all the simulation code for the IPs and then write my own simulation script.


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  7. #7
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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    Both the errors have been rectified by
    1) Avoiding spaces in the absolute path of the project as rightly said by ads-ee
    That space in the name is breaking the auto generated scripts created when running a simulation from the Vivado GUI.
    2) By providing the absolute path of the text file. In ISE, I was placing the file in project's current directory, and then just providing the name only. But in vivado, we need to provide the whole path, otherwise, vivado deletes the file on its own.



    •   Alt14th September 2017, 10:22

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    Re: "ERROR: [Common 17-165] Too many positional options when parsing

    Quote Originally Posted by rafimiet View Post
    2) By providing the absolute path of the text file. In ISE, I was placing the file in project's current directory, and then just providing the name only. But in vivado, we need to provide the whole path, otherwise, vivado deletes the file on its own.
    It might be that the simulation is running in a different folder than you expect. This is why I always like to run simulations manually (although I have never used the vivado simulator, I never use internal projects in Modelsim or ActiveHDL)



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