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OTA Input Voltage divider less noisy

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olrac_s

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Hello to everybody!

I've a situation like this one:

CLASSIC_P_OTA.png

Due to the limited input swing range I cannot apply a signal biased at 1.2V if the power supply Vdd is at 1.5V. So I'm obliged to use a voltage divider at one input of the differential stage.

For my application ( a low noise LDO ) i cannot use that resistors because they are too noisy. But at the same time I would like to maintain the same topology (n MOS mirror) for noise and PSRR performances.


How can I extend input swing? or shift the level of the input introducing less noise?


Thanks so much to everybody!
 

At least you could reduce the noise bandwidth to your required control (regulation) bandwidth by a capacitor in parallel to the input.
 

Hi Erikl, Thanks so much for your reply.

Yes but considering this simply LDO schematic:
p_general.png

In the voltage divider node, which coincide with the output node is located my dominant pole. I cannot reduce the bandwidth or I ll have some overshot problem if the regulator will not be fast enough and I cannot integrate a big capacitance. Max some pF.
 

olrac_s said:
... I cannot integrate a big capacitance. Max some pF.
Click to expand...

Sure, like any chip designer. But 1MΩ*1pF results in a pole frequency of ≈160kHz, which should be far enough from your dominant pole, and still fast enough for the regulation. At least it will attenuate all the noise > 1Mhz with additional -20dB/decade. Check by simulation, if it's worth the cap area.
 

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