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    cross couple charge pump, waveform inquiry? (circuit and waveforms are attached)

    Hi,

    I am using 6 modules from cross-coupled charge pumps, CCCP, ( circuit attached), to generate >1.8V out of 0.5V and I am using 1pF for all caps including output and minimum transistor sizes, nMOS (1.5um/0.6um) and pMOS (1.5um/0.6um)
    These CCCP are simulated twice, first case with body terminals of nMOS connected to zero (there will be body effect). Second case with Vsb=0 (no body effect). The simulation waveforms are attached.

    My questions about the body effect in these waveforms? I was expecting to see much difference for Vout voltage in steady-state because of higher Vth for nMOS devices in the circuit, but it was not the case! the difference is close to 0.1V
    The only difference i can see is that with body effect, case 1, the settling time for Vout is much much higher than case 2.

    •   Alt12th September 2017, 16:36

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    Re: cross couple charge pump, waveform inquiry? (circuit and waveforms are attached)

    Quote Originally Posted by bio_man View Post
    with body effect, case 1, the settling time for Vout is much much higher than case 2.
    Because for case 1 (nMOS Vsb>0) Vt_eff is higher than Vt in case 2 (Vsb=0). So its path resistance (for same Vgs) is higher --> greater RC time constant.


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    •   Alt14th September 2017, 13:45

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    Re: cross couple charge pump, waveform inquiry? (circuit and waveforms are attached)

    So, it means the Body effect ( Vsb!=0) will affect only the transient?

    Previously, I thought the body effect will lower the output voltage because the Vgs in case 1 (Vsb!=0) is not high enough to let the nMOS conduct. That's why I was thinking to increase the number of modules to compensate for this voltage loss.



    •   Alt14th September 2017, 14:03

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    Re: cross couple charge pump, waveform inquiry? (circuit and waveforms are attached)

    Quote Originally Posted by bio_man View Post
    ... I thought the body effect will lower the output voltage because the Vgs in case 1 (Vsb!=0) is not high enough to let the nMOS conduct.
    It still conducts, but as the difference Vgs-Vt_eff is lower than Vgs-Vt , it will allow just a lower Id current, so it will take longer to load the caps. Probably, the final CP output voltage will also be a little bit lower, about n*(Vt_eff - Vt). I think, your above diagram shows this, too.


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