tanish
Junior Member level 2
hello.
I have a verilog code for r single port ram :
when I do the xst analyse in ISE I have this result:
Minimum period: 1.535ns (Maximum Frequency: 651.529MHz)
Minimum input arrival time before clock: 3.472ns
Maximum output required time after clock: 3.597ns
Maximum combinational path delay: No path found
and everything is ok when I run post place route simulatin and I can see the write and read operations
but when I choose word's length like this :
when I run xst analyse I have this ressult:
Minimum period: No path found
Minimum input arrival time before clock: 2.324ns
Maximum output required time after clock: 5.000ns
Maximum combinational path delay: No path found
there is no value for minimum period
and when I run post place route simulation all results are zero(read operation).
could anyone help me?
I really need to write a code which word's length is at least 256 and it should be high speed enough.
I used spartan 6 XC6SLX75 for my project.
and this is my testbench:
I have a verilog code for r single port ram :
Code Verilog - [expand] | |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 | module RAM ( clk, we, en, addr, din, dout ); input clk; input we; input en; input [5:0] addr; input [15:0] din; output [15:0] dout; reg [15:0] RAM [63:0]; reg [15:0] dout; always @(posedge clk) begin if (en) begin case (we) 1'b1 : RAM[addr] <= din; 1'b0 : dout <= RAM[addr]; endcase end end endmodule |
when I do the xst analyse in ISE I have this result:
Minimum period: 1.535ns (Maximum Frequency: 651.529MHz)
Minimum input arrival time before clock: 3.472ns
Maximum output required time after clock: 3.597ns
Maximum combinational path delay: No path found
and everything is ok when I run post place route simulatin and I can see the write and read operations
but when I choose word's length like this :
Code Verilog - [expand] | |
1 | reg [63:0] RAM [63:0]; |
when I run xst analyse I have this ressult:
Minimum period: No path found
Minimum input arrival time before clock: 2.324ns
Maximum output required time after clock: 5.000ns
Maximum combinational path delay: No path found
there is no value for minimum period
and when I run post place route simulation all results are zero(read operation).
could anyone help me?
I really need to write a code which word's length is at least 256 and it should be high speed enough.
I used spartan 6 XC6SLX75 for my project.
and this is my testbench:
Code Verilog - [expand] | |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 | module testbench; // Inputs reg clk; reg we; reg en; reg [5:0] addr; reg [31:0] din; // Outputs wire [31:0] dout; // Instantiate the Unit Under Test (UUT) state_metric_RAM uut ( .clk(clk), .we(we), .en(en), .addr(addr), .din(din), .dout(dout) ); always begin clk = 1'b0; #5; clk = 1'b1; #5; end initial begin en = 1'b1; #10; end initial begin #107; din = 32'h0000111d; addr = 6'b000100; we = 1'b1; #11; din = 32'h00000011; addr = 6'b010000; we = 1'b1; #10; din = 32'h0101abcd; addr = 6'b000010; we = 1'b1; #10; addr = 6'b000100; we = 1'b0; #10; addr = 6'b010000; we = 1'b0; #10; addr = 6'b000010; we = 1'b0; #10; addr = 6'b000100; we = 1'b0; #10; end endmodule |