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  1. #1
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    word's length of single port RAM

    hello.
    I have a verilog code for r single port ram :
    Code Verilog - [expand]
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    module RAM (
    clk,
    we,
    en,
    addr,
    din,
    dout
    );

    input clk;
    input we;
    input en;
    input [5:0] addr;
    input [15:0] din;
    output [15:0] dout;


    reg [15:0] RAM [63:0];
    reg [15:0] dout;


    always @(posedge clk)
    begin
    if (en)
    begin
    case (we)
    1'b1 : RAM[addr] <= din;

    1'b0 : dout <= RAM[addr];
    endcase
    end
    end
    endmodule



    when I do the xst analyse in ISE I have this result:

    Minimum period: 1.535ns (Maximum Frequency: 651.529MHz)
    Minimum input arrival time before clock: 3.472ns
    Maximum output required time after clock: 3.597ns
    Maximum combinational path delay: No path found

    and everything is ok when I run post place route simulatin and I can see the write and read operations

    but when I choose word's length like this :
    Code Verilog - [expand]
    1 reg [63:0] RAM [63:0];



    when I run xst analyse I have this ressult:

    Minimum period: No path found
    Minimum input arrival time before clock: 2.324ns
    Maximum output required time after clock: 5.000ns
    Maximum combinational path delay: No path found

    there is no value for minimum period

    and when I run post place route simulation all results are zero(read operation).

    could anyone help me?
    I really need to write a code which word's length is at least 256 and it should be high speed enough.

    I used spartan 6 XC6SLX75 for my project.

    and this is my testbench:
    Code Verilog - [expand]
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    module testbench;

    // Inputs
    reg clk;
    reg we;
    reg en;
    reg [5:0] addr;
    reg [31:0] din;

    // Outputs
    wire [31:0] dout;

    // Instantiate the Unit Under Test (UUT)
    state_metric_RAM uut (
    .clk(clk),
    .we(we),
    .en(en),
    .addr(addr),
    .din(din),
    .dout(dout)
    );

    always begin
    clk = 1'b0;
    #5;
    clk = 1'b1;
    #5;
    end

    initial begin
    en = 1'b1;
    #10;
    end
    initial begin
    #107;
    din = 32'h0000111d;
    addr = 6'b000100;
    we = 1'b1;
    #11;
    din = 32'h00000011;
    addr = 6'b010000;
    we = 1'b1;
    #10;
    din = 32'h0101abcd;
    addr = 6'b000010;
    we = 1'b1;
    #10;
    addr = 6'b000100;
    we = 1'b0;
    #10;
    addr = 6'b010000;
    we = 1'b0;
    #10;
    addr = 6'b000010;
    we = 1'b0;
    #10;
    addr = 6'b000100;
    we = 1'b0;
    #10;
    end



    endmodule

    •   Alt12th September 2017, 14:24

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  2. #2
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    Re: word's length of single port RAM

    Probably the the first code build the ram with distributed ram, and the 2nd used a BRAM, so there were no LUTs used, so it cannot time the design between registers.


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    •   Alt12th September 2017, 15:23

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  3. #3
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    Re: word's length of single port RAM

    so what should I do?



    •   Alt12th September 2017, 15:27

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    Re: word's length of single port RAM

    That is not the exactly the same as the inferred RAM template provided by ISE see this post in another thread. Your testbench code is for 32-bit data, the RAM module is for 16-bits, and then you want to use 64-bits? Which is it what did you simulate together because nothing you've shown matches.

    - - - Updated - - -

    Quote Originally Posted by TrickyDicky View Post
    Probably the the first code build the ram with distributed ram, and the 2nd used a BRAM, so there were no LUTs used, so it cannot time the design between registers.
    Good point, but the depth is usually what defines the selection of distributed and BRAM and that didn't change. It would help if the OP showed the implementation resource report summary to see what resources it used. As they ran a post route simulation and it doesn't produce output data, seems to suggest something else is wrong. Without a simulation log/transcript output to see if there is an issue with the compilation and/or simulation itself, it's impossible to determine the cause of the simulation failure.



  5. #5
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    Re: word's length of single port RAM

    oh that was a mistake of copy paste.thats not the problem if you correct them and then run post simulate you can observe the problem. I changed the length to generate xst reports but I forgot to change testbench.
    it was just a copy paste mitake.
    and the code is from xilinx pdf tutorials(Synthesis and Simulation Design Guide):
    I changed the if statement with case statement to have a faster RAM.
    Click image for larger version. 

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    please help me because I can't continue my project.



    •   Alt12th September 2017, 17:20

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  6. #6
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    Re: word's length of single port RAM

    Using a case statement instead of the if statement isn't going to make the hardware faster. In this case using no change mode requires logic on the output side of the RAM that makes it slower.

    Without a place and route netlist, a transcript/log output of the simulation, or some other useful information (other than the Verilog code, which simulates though the we is U at the start of simulation due to lack of initializing it in the testbench) there isn't much help anyone can give besides guessing.


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