[Moved]: Div 2/3 prescaler with 50% duty cycle

Hi,

I need to design a DIVIDE 2/3 prescaler (as part of the DIVN multi modulus divider in a PLL) with 50% duty cycle. I am aware of the usual designs in which one of the pulses is swallowed, the output of the divider does not have 50% duty cycle. Any suggestions on this please.

Thank you,
mvj

Guess, once again G00GLE is your friend. E.g. this MIT lecture, pp. 31..46 .

Thank you Erikl, I have been looking around and already went through link you gave..unfortunately the duty cycle is not 50% in any of the ideas presented..So, I was wondering if there is a way to do it..

Thank you,
mvj

Why does the PLL require a 50% duty-cycle?

A simple way would be use double the input frequency (input doubler, if necessary), then divide by 3, then divide by 2 , s. this paper, Figure.10. Of course needs more power.

Perhaps it isn't even necessary to have 50% duty cycle, because only the rising edges are used for the PFD ? See this article, search for duty.

Ok - I've seen too late: crutschow asked the same question.

Hi All,
Well..actually I did not make myself clear..sorry..
I need the 2/3 prescaler to use it as part of the DIVIDER that divides the PLL output to generate the required output clock frequency. Based upon the output frequency required I will change the division ration of the divider. A multi modulus divider does not give a 50% duty cycle unless i can make the "divide by 3" a 50% duty cycle output.

Thank you,
mvj

I still don't understand why you need a 50% duty-cycle. :???:

As long as you are talking about a prescaler without an oscillator on its own or similar signal generating means, the output waveform can only change state at the edges of the input signal.

You may want to sketch a timing diagram and realize that a 2/3 divider with 50 % duty cycle isn't feasible because it introduces new edge events.

A 2/3 divider with 33 or 66% duty cycle can be made if it utilizes both input signal edges, not achievable with standard FF circuits.

You should clarify which circuit design techniques are available for your project, also mention the intended operation frequency.

Hi,

I need the 2/3 prescaler to use it as part of the DIVIDER that divides the PLL output to generate the required output clock frequency

Click to expand...

This divider is for:
* the PLL feedback loop?
* or for the clock output to the application?

Feedback loop:
Usually a PLL has two divider. One for the input (reference) frequency called "d" and the other in the feedback called "m".
--> multiply your initial "d" value with 2 , and your initial "m" value with 3.
Example: Ref_clock = 2MHz--> output = 3MHz

Application clock:
Usually a PLL has two divider. One for the input (reference) frequency called "d" and the other in the feedback called "m".
--> multiply your initial "d" value with 3 , and your initial "m" value with 2.
Example: Ref_clock = 3MHz--> output = 2MHz.

****
If this doesn't help, please give these informations:
* input (reference) clock frequency
* desired output clock frequency (to application)
* used PLL circuit

Klaus

Hi All,

Please find below more information regarding the same as asked..

There is a PLL, its output clock is divided down by an "OUTPUT DIVIDER"and used as clock for an application(s).
Now, the application uses both rising and falling edges of the clock it is provided with and the clock needs to be of 50% duty cycle.
The application needs different clock frequencies in different scenarios (now, one might think that this change in frequency can be achieved by varying PLL frequency but I cannot do this due to other system level reasons). So, I need an output divider whose division value can be changed i.e. a multi modulus divider. This is usually implemented using div 2/3 cells (divider that can divide by 2 or 3 based on an input control) in cascade e.g. shown on slide 34, 35 and 36 of the MIT lecture mentioned by Erikl. Now the problem with this approach is that the output is not 50% duty cycle. So, I would like to know if there is a way to tweak the design example or some other topology which would give 50% duty cycle.
e.g. I have a PLL wiht 2GHz output, from this i need to generate two clocks one at 2GHz/20 and the other is 2GHz/21 but both need to be 50% duty cycle.

Any suggestions please..

Thank you,
mvj

Hi,

it is more clearely now.

With a divider of 2/3 there is the problem that you need an output clock edge where there is no clock edge at the input signal.
But indeed you want to divide by 21. And now there is always a clock edge, but one rising and one falling at the input signal.

I can´t give you a solution for your ASIC, but I´d say with 21 it is possible but with 2/3 not.
****
To use 2/3 with the use of the input clock edges gives a duty cycle of 33% or 67%. This is an awful clock.
And if you want it DC free you need to continously jump between 33% and 67%. This looks even more awful.

But with divide by 21 and using only rising clock edges you get a 10 input_clock to 11 input_clock ratio. This is a duty cycle of 47.6% ... not that bad. And it is likely that such a deviation can be accepted.
Mind that you will never get a pure 50.0000% duty cycle. There is alwys some error, jitter .. and so on.

****
Another solution is to run the PLL with 4GHz and divide by 40 and 42. This means you may use standard didvider.

Klaus

Hi Klaus,

Thank you for your suggestions and regarding..

But with divide by 21 and using only rising clock edges you get a 10 input_clock to 11 input_clock ratio. This is a duty cycle of 47.6% ... not that bad. And it is likely that such a deviation can be accepted.
Mind that you will never get a pure 50.0000% duty cycle. There is alwys some error, jitter .. and so on.

Click to expand...

After 10 input clock cycles, in the 11th clock cycle would it be possible to use the falling edge of the input clock to make the output clock go low, in this way..the output clock signal will have 50% duty cycle..

Please suggest..

Thank you,
mvj

I actually misunderstood the term divide 2/3. Divide by three with (roughly) 50 percent duty cycle is feasible with dual edge clocked FFs or a circuit emulating dual clock sensitivity (a combination of regular FFs and combinational circuits).

Hi,

in your post#12 you are addressing me.

After 10 input clock cycles, in the 11th clock cycle would it be possible to use the falling edge of the input clock to make the output clock go low, in this way..the output clock signal will have 50% duty cycle..

Please suggest..

Click to expand...

But I already gave you my best answer:

But indeed you want to divide by 21. And now there is always a clock edge, but one rising and one falling at the input signal.

I can´t give you a solution for your ASIC, but I´d say with 21 it is possible but with 2/3 not.

Click to expand...

You need to find an ASIC expert for this. At least one that can say if this really is possible or not.

I did similar with a CPLD. It realized it with a counter and an combinatorial logic. It was designed glitch-free because the signals overlapped.
But I´m not sure if the same is possible with an ASIC .. especially at this high frequencies.

Klaus