# Initializing a very long vector with some repetition

1. ## Initializing a very long vector with some repetition

I have to initialize a very long vector in the pattern such as
x(0*64 TO 0*64+15) = '1';
x(1*64 TO 1*64+15) = '1';
x(2*64 TO 2*64+15) = '1';
...
x(15*64 TO 15*64+15) = '1';
What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.

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2. ## Re: Initializing a very long vector with some repetition

Is this VHDL, as it has syntax errors?
Where is this initialisation done? Can you post the real code, or a complete example rather than just a snippet?

3. ## Re: Initializing a very long vector with some repetition

The vhdl code is as follows:
 Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 GENERIC(LLrow: INTEGER := 16); SIGNAL b0 : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0) := (OTHERS => '0') ; variable row : INTEGER RANGE 1 TO N := 1; variable addr2_2 : INTEGER RANGE 0 TO N*N-1 := 0; ...                                           if row <= LLrow then                                             b0(addr2_2 + LLrow-1 downto addr2_2) <= (OTHERS => '1');                                             row := row + 1;                                             addr2_2 := addr2_2 + N/2;                                         end if;
As I try to synthesis this, it never comes out of running synthesis.

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4. ## Re: Initializing a very long vector with some repetition

Please post the whole code, or complete example showing the problem.

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5. ## Re: Initializing a very long vector with some repetition

if row <= LLrow then
row := row + 1;
end if;
This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.

6. ## Re: Initializing a very long vector with some repetition

Originally Posted by dpaul
This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.
Don't you know if you write VHDL using variables it behaves more like software

7. ## Re: Initializing a very long vector with some repetition

dpaul... This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.
Don't you know if you write VHDL using variables it behaves more like software
I have a very long code using Finite State Machine. Here I attach the code. The code is sequential, so using signal provides output only on the next clock cycle. Also I sometimes need to update the value of an object within the same loop twice, which is not possible with signals, so I use variables.
Please check my code design strategy and suggest me how to make my code efficient

8. ## Re: Initializing a very long vector with some repetition

Originally Posted by rafimiet
I have to initialize a very long vector in the pattern such as

What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.
Without making things more complicated, lets come to your original problem....

Why don't you use a generate statement to achieve the above(assuming x is a signal of type std_logic_vector)?

array_gen : for i in 0 to 15 generate
x(i*64 TO i*64+15) <= (others => '1');
end generate array_gen;

As Tricky mentioned in #2, it would be interesting to know what x is is!

I can't go through your long code, but...
Also I sometimes need to update the value of an object within the same loop twice, which is not possible with signals, so I use variables.
This is not good. Allow extra states (I am sure your design can live with 2 or 3 clks of extra latency), let the signals update on the next clk, and then check their values in a new state.

If you want FSM coding style from Xilinx- https://www.xilinx.com/support/docum...-pdf/lab10.pdf

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9. ## Re: Initializing a very long vector with some repetition

This post is all very confusing, as I dont understand how the original question relates to the huge code posted.

Why don't you use a generate statement to achieve the above(assuming x is a signal of type std_logic_vector)?

array_gen : for i in 0 to 15 generate
x(i*64 TO i*64+15) <= (others => '1');
end generate array_gen;
This wont work, as this is not an initialisation, but just driving all the bits of X to constant 1. Its not clear what the OP means by initialisation - do you mean power up initialisation or initialisation as part of your running design. ie something writes all the addresses of a ram?

Please clarify exactly what the problem is.