# Initializing a very long vector with some repetition

1. ## Initializing a very long vector with some repetition

I have to initialize a very long vector in the pattern such as
x(0*64 TO 0*64+15) = '1';
x(1*64 TO 1*64+15) = '1';
x(2*64 TO 2*64+15) = '1';
...
x(15*64 TO 15*64+15) = '1';
What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.

•

2. ## Re: Initializing a very long vector with some repetition

Is this VHDL, as it has syntax errors?
Where is this initialisation done? Can you post the real code, or a complete example rather than just a snippet?

3. ## Re: Initializing a very long vector with some repetition

The vhdl code is as follows:
```Code VHDL - [expand]1
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GENERIC(LLrow: INTEGER := 16);
SIGNAL b0 : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0) := (OTHERS => '0') ;
variable row : INTEGER RANGE 1 TO N := 1;
variable addr2_2 : INTEGER RANGE 0 TO N*N-1 := 0;
...

if row <= LLrow then
row := row + 1;
end if;```
As I try to synthesis this, it never comes out of running synthesis.

4. ## Re: Initializing a very long vector with some repetition

Please post the whole code, or complete example showing the problem.

•

5. ## Re: Initializing a very long vector with some repetition

if row <= LLrow then
row := row + 1;
end if;
This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.

6. ## Re: Initializing a very long vector with some repetition

Originally Posted by dpaul
This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.
Don't you know if you write VHDL using variables it behaves more like software

7. ## Re: Initializing a very long vector with some repetition

dpaul... This part gives me a headache...plz use signals!
Stop using variables in the synthesizable part of your design. You can do everything with signals.
Don't you know if you write VHDL using variables it behaves more like software
I have a very long code using Finite State Machine. Here I attach the code. The code is sequential, so using signal provides output only on the next clock cycle. Also I sometimes need to update the value of an object within the same loop twice, which is not possible with signals, so I use variables.
Please check my code design strategy and suggest me how to make my code efficient
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    14:39:53 07/27/2017
-- Design Name:
-- Module Name:    FSM_all - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity FSM_all is
GENERIC (L : INTEGER := 3;                  -- L is level of DWT
N : integer := 256;             -- N x N is image size
logN : INTEGER := 8;            -- log10(N)/log10(2) gives n bits that can address N
LLrow : INTEGER := 16;          -- N/2^(L+1) Range (0 TO LLrow-1)
word_length : integer := 11);
Port ( rst,clk : in  STD_LOGIC;
i : in  STD_LOGIC_VECTOR (7 downto 0);
out_en : OUT std_logic;
y : out  STD_LOGIC_VECTOR (word_length-1 downto 0));
end FSM_all;

architecture Behavioral of FSM_all is
-- SRA FUNCTION --
function "sra" (l : signed; r : natural) return signed is
alias l_a : signed(l'length-1 downto 0) is l;
begin
return resize(l_a, l_a'length + r)(l_a'length+r-1 downto r);
end function "sra";

--- RAM SIGNALS ---
TYPE ram_type IS ARRAY (N*N-1 DOWNTO 0) OF STD_LOGIC_VECTOR(word_length-1 DOWNTO 0);
SIGNAL RAM1: ram_type;
SIGNAL RAM2: ram_type;
SIGNAL we1,en1,we2,en2 : STD_LOGIC :='0';
SIGNAL di1,do1,di2,do2 : STD_LOGIC_VECTOR(word_length-1 DOWNTO 0):= (OTHERS => '0');
--- FSM SIGNALS ---
SIGNAL pr_state: state;

--- DWT SIGNALS ---
SIGNAL s1,x2k,s2,s23,s3 : signed(word_length-1 downto 0);

--- DEBUGGING SIGNALS ---
SIGNAL db_addr : INTEGER RANGE 0 TO N*N/4-1 := 0;

--- SPIHT SIGNALS ---
---(N*N/(2**(2*L))-1) L=3,N=256 =>1023
SIGNAL b0 : STD_LOGIC_VECTOR(N*N/4 - 1 downto 0) := (OTHERS => '0') ;--Current block significant
SIGNAL b1, b2 : STD_LOGIC_VECTOR(N*N/16 - 1 downto 0);-- b1:if all des sig or not, b2: typeA or B
SIGNAL threshold : INTEGER RANGE 0 TO word_length-1;
SIGNAL init_thrsh : signed(word_length-1 downto 0) := (OTHERS => '0');
SIGNAL b0_addr : INTEGER RANGE 0 TO N*N/4-1 := 0;

begin
--- RAM1 INITIALIZATION HERE ---
ram1_init : PROCESS(clk)
BEGIN
if clk'event AND clk = '1' then
if en1 = '1' then
if we1 = '1' then
else
end if;
end if;
end if;
END PROCESS ram1_init;

--- RAM2 INITIALIZATION HERE ---
ram2_init : PROCESS(clk)
BEGIN
if clk'event AND clk = '1' then
if en2 = '1' then
if we2 = '1' then
else
end if;
end if;
end if;
END PROCESS ram2_init;

----- FSM STARTS FROM HERE ----
----- Main Section of FSM -----
Main:           PROCESS(clk,rst)
----DWT VARIABLES----
variable di_temp,di_temp1 : STD_LOGIC_VECTOR(word_length-1 downto 0);
variable adr,ram_out,ram_out1,alt1,alt5 : STD_LOGIC := '0';
variable ram_out2 : STD_LOGIC_VECTOR(1 downto 0) := "00";
variable v1,v3 : signed(word_length-1 downto 0) := (OTHERS => '0');
variable v2 : signed(word_length-1 downto 0);
variable count_1,count : INTEGER RANGE 0 TO 7 := 0;
variable row,col1,col2,c_col1,c_col2 : INTEGER RANGE 1 TO N := 1;
variable M : INTEGER RANGE 0 TO N := N;
variable level : INTEGER RANGE 0 TO 5 := 1;
variable thrsh : STD_LOGIC_VECTOR(word_length-2 downto 0);

----SPIHT VARIABLES----

BEGIN

IF clk'EVENT AND clk = '1' THEN
IF rst = '0' THEN
CASE pr_state IS
------- DWT Stages -----------
WHEN fill_ram => -- Take 1D DWT Directly and fill into RAM2
out_en <= '0';
di_temp(word_length-1 downto 8) := (OTHERS => '0');
--      di_temp(5 downto 0) := (OTHERS => '0');
di_temp(7 downto 0) := i;
ram_out := '0';count := 0;
end if;
if count = 0 then
count := count + 1;
elsif alt5 = '1' then
s1 <= signed(di_temp1);
x2k <= signed(di_temp);
v1 := s1 + x2k;
s2 <= v1 sra 1;
v2 := s1 - x2k;
s23 <= v2 sra 1;
alt5 := NOT alt5;
else
alt5 := NOT alt5;
di_temp1 := di_temp;
end if;
s3 <= s23;
if ram_out = '0' then
if count_1 >= 6 then
we2 <= '1'; en2 <= '1';
di2 <= std_logic_vector(s2);
ram_out := '1';
else
count_1 := count_1 + 1;
end if;
else
we2 <= '1'; en2 <= '1';
di2 <= std_logic_vector(s3);
ram_out := '0';
pr_state <= dwt2d;
alt5 := '0';
count_1 := 0;
s1 <= (OTHERS => 'Z');s2 <= (OTHERS => 'Z');
s3 <= (OTHERS => 'Z');
x2k <= (OTHERS => 'Z');
end if;
end if;

WHEN dwt1d =>
out_en <= '0';
we1 <= '0';
count := 0;
ram_out := '0';alt5 := '0';
di_temp1 := (OTHERS => 'Z');
elsif col1 <= M then
if row < M then
if row = 1 then
end if;
row := row + 1;
else
row := 1;
if col1 < M then
end if;
col1 := col1 + 1;
end if;
end if;
if count <= 1 then
count := count + 1;
elsif alt5 = '1' then
s1 <= signed(di_temp1);
x2k <= signed(do1);
v1 := s1 + x2k;
s2 <= v1 sra 1;
v2 := s1 - x2k;
s23 <= v2 sra 1;
alt5 := NOT alt5;
else
alt5 := NOT alt5;
di_temp1 := do1;
end if;
s3 <= s23;
if ram_out = '0' then
if count_1 >= 6 then
we2 <= '1'; en2 <= '1';
di2 <= std_logic_vector(s2);
ram_out := '1';
else
count_1 := count_1 + 1;
end if;
else
we2 <= '1'; en2 <= '1';
di2 <= std_logic_vector(s3);
ram_out := '0';
pr_state <= dwt2d;
alt5 := '0';
count_1 := 0;
end if;
end if;

WHEN dwt2d =>
out_en <= '0';
we2 <= '0';
row := 1;
col1 := 1;
ram_out := '0';
count_1 := 0;count := 0;
s3 <= (OTHERS => 'Z');
elsif row < M then
row := row + 1;
elsif row = M then
if col1 < M/2 then
col1 := col1 + 1;
row := 1;
elsif col1 = M/2 then
col1 := col1 + 1;
col2 := 1;
row := 1;
else
if col2 < M/2 then
col2 := col2 + 1;
row := 1;
end if;
end if;
end if;
if count <= 1 then
count := count + 1;
elsif alt5 = '1' then
s1 <= signed(di_temp1);
x2k <= signed(do2);
v1 := s1 + x2k;
s2 <= v1 sra 1;
v2 := s1 - x2k;
s23 <= v2 sra 1;
alt5 := NOT alt5;
else
alt5 := NOT alt5;
di_temp1 := do2;
end if;
s3 <= s23;
if s23(word_length-1) = '0' then
if s23 > v3 then
v3 := s23;
end if;
end if;
if s2(word_length-1) = '0' then
if s2 > v3 then
v3 := s2;
end if;
end if;
init_thrsh <= v3;
if ram_out2 = "00" then
if count_1 >= 6 then
we1 <= '1'; en1 <= '1';
di1 <= std_logic_vector(s2);
if c_col1 = 1 then
c_col1 := c_col1 + 1;
elsif c_col1 = M/2 then
a_temp := a_temp + 1;
c_col1 := 1;
else
c_col1 := c_col1 + 1;
end if;
ram_out2 := "01";
else
count_1 := count_1 + 1;
a_temp := 0;
end if;
elsif ram_out2 = "01" then
we1 <= '1'; en1 <= '1';
ram_out2 := "00";
if c_col2 < M/2 then
if c_col2 = 1 then
end if;
c_col2 := c_col2 + 1;
else
if addr1_2 = N*(M-1) + M/2 -1 then
ram_out2 := "10";
count_1 := 0;
c_col1 := 1;
c_col2 := 1;
alt1 := '0';
else
end if;
c_col2 := 1;
end if;
di1 <= std_logic_vector(s3);
elsif ram_out2 = "10" then
we1 <= '1'; en1 <= '1';
if c_col1 < M/2 then
if c_col1 = 1 then
end if;
c_col1 := c_col1 + 1;
else
c_col1 := 1;
end if;
di1 <= std_logic_vector(s2);
ram_out2 := "11";
else
we1 <= '1'; en1 <= '1';
ram_out2 := "10";
if c_col2 < M/2 then
if c_col2 = 1 then
end if;
c_col2 := c_col2 + 1;
else
if addr1_4 = N*(M-1) + M - 1 then
ram_out2 := "00";
count_1 := 0;
if level < L then
pr_state <= dwt1d;
level := level + 1;
alt5 := '0';
M := M/2;
else
pr_state <= initialize_SPIHT;
alt5 := '0';count_1 := 0;
end if;
end if;
c_col2 := 1;
end if;
di1 <= std_logic_vector(s3);
end if;
------- SPIHT STAGES ----------------
------- REFINEMENT PASS -------------
WHEN initialize_SPIHT =>
if row <= 2*LLrow then
row := row + 1;
if count_1 <= word_length-1 then
if init_thrsh(word_length-1-count_1) = '1' then
threshold <= word_length-1-count_1;
else
count_1 := count_1 + 1;
end if;
end if;

else
end if;

we1 <= '0';we2 <= '0';
else
end if;
else
else
end if;
end if;
else
pr_state <= sorting;
end if;

if count = 0 then
elsif count = 2 then
else
end if;
pr_state <= ref_bitstream;

WHEN ref_bitstream =>
if do1(word_length-1) = '1' then
di_temp := std_logic_vector(-signed(do1));
else
di_temp := do1;
end if;
if di_temp(threshold) = '1' then ---SIGNIFICANT AT THIS THRESHOLD
thrsh := (OTHERS => '0');
thrsh(threshold) := '1';
if di_temp(word_length-2 downto 0) > thrsh then
a_temp := 1;
else
a_temp := 0;
end if;
if  a_temp = 0 then ---NOT ALREADY SIGNIFICANT COEFFICIENT
if addr2_1 = word_length-1 then --- can hold only one more bit
di2 <= di_temp1;
we2 <= '1';
di2 <= di_temp1;
we2 <= '1';
else
we2 <= '0';
end if;
di2 <= di_temp1;
we2 <= '1';
else
we2 <= '0';
end if;
end if;
else --- NOT SIGNIFICANT AT THIS THRESHOLD
di2 <= di_temp1;
we2 <= '1';
else
we2 <= '0';
end if;
end if;
if count = 3 then
count := 0;
else
count := count + 1;
end if;
pr_state <= sorting;
WHEN sorting =>
pr_state <= idwt1d;

-------- IDWT STAGES ----------------
WHEN idwt1d =>
we1 <= '0';en1 <= '1';
out_en <= '0';
ram_out2 := "00";
ram_out1 := '0';
count_1 := 0;count := 0;
alt1 := '0';c_col2 := 1;
c_col1 := 1; alt5 := '0';
--      s1 <= (OTHERS => 'Z'); do1 <= (OTHERS => 'Z');do1 <= (OTHERS => 'Z');
end if;
if ram_out2 = "00" then
we1 <= '0'; en1 <= '1';
if c_col1 = 1 then
c_col1 := c_col1 + 1;
elsif c_col1 = M/2 then
a_temp := a_temp + 1;
c_col1 := 1;
else
c_col1 := c_col1 + 1;
end if;
ram_out2 := "01";
elsif ram_out2 = "01" then
we1 <= '0'; en1 <= '1';
ram_out2 := "00";
if c_col2 < M/2 then
if c_col2 = 1 then
end if;
c_col2 := c_col2 + 1;
else
if addr1_2 = N*(M-1) + M/2 -1 then
ram_out2 := "10";
c_col1 := 1;
c_col2 := 1;
alt1 := '0';
else
end if;
c_col2 := 1;
end if;
elsif ram_out2 = "10" then
we1 <= '0'; en1 <= '1';
if c_col1 < M/2 then
if c_col1 = 1 then
end if;
c_col1 := c_col1 + 1;
else
c_col1 := 1;
end if;
ram_out2 := "11";
else
we1 <= '0'; en1 <= '1';
ram_out2 := "10";
if c_col2 < M/2 then
if c_col2 = 1 then
end if;
c_col2 := c_col2 + 1;
else
if addr1_4 = N*(M-1) + M - 1 then
ram_out2 := "11";
else
c_col2 := 1;
end if;
end if;
end if;
if count <= 1 then
count := count + 1;
elsif alt5 = '1' then
s1 <= signed(di_temp1);
x2k <= signed(do1);
s2 <= s1 + x2k;
s23 <= s1 - x2k;
alt5 := NOT alt5;
else
alt5 := NOT alt5;
di_temp1 := do1;
end if;
s3 <= s23;
if count_1 >= 6 then
we2 <= '1';
if ram_out = '0' then
di2 <= std_logic_vector(s3);
ram_out := '1';
else
di2 <= std_logic_vector(s2);
ram_out := '0';
end if;
if count_1 <= 7 then
count_1 := count_1 + 1;
else
if row < M then
row := row + 1;
elsif row = M then
if col1 < M/2 then
col1 := col1 + 1;
row := 1;
elsif col1 = M/2 then
col1 := col1 + 1;
col2 := 1;
row := 1;
else
if col2 < M/2 then
col2 := col2 + 1;
row := 1;
elsif col2 = M/2 then
pr_state <= idwt2d;
end if;
end if;
end if;
end if;
else
count_1 := count_1 + 1;we2 <= '0';
row := 1;col1 := 1;col2 := 1;ram_out := '0';
end if;

WHEN idwt2d =>
out_en <= '0';
we2 <= '0';
count_1 := 0;
count := 0;
col1 := 1;
ram_out := '0';col1 := 1;ram_out1 := '0';
end if;
if ram_out = '0' then
ram_out := '1';
else
ram_out := '1';
else
ram_out := '0';
end if;
end if;
if count <= 1 then
count := count + 1;
elsif alt5 = '1' then
s1 <= signed(di_temp1);
x2k <= signed(do2);
s2 <= s1 + x2k;
s3 <= s1 - x2k;
alt5 := NOT alt5;
else
alt5 := NOT alt5;
di_temp1 := do2;
end if;
if count_1 >= 6 then
we1 <= '1';en1 <= '1';
if ram_out1 = '0' then
di1 <= std_logic_vector(s2);
ram_out1 := '1';
else
di1 <= std_logic_vector(s3);
ram_out1 := '0';
end if;
if count_1 <= 6 then
count_1 := count_1 + 1;
elsif col1 <= M then
if row < M then
if row = 1 then
end if;
row := row + 1;
else
row := 1;
if col1 < M then
end if;
col1 := col1 + 1;
end if;
else
if level = L then
pr_state <= output;
else
pr_state <= idwt1d;
level := level + 1;
M := 2*M;
end if;
end if;
else
count_1 := count_1 + 1;
addr1 <= 0;a_temp := 0;row := 1;
alt1 := '0'; col1 := 1;
end if;
----- OUTPUT STAGES ------
WHEN output =>
out_en <= '1';
we1 <= '0';en1 <= '1';
if do1(word_length-1) = '1' then
y <= (OTHERS => '0');
else
y(word_length-1 downto 0) <= do1(word_length-1 downto 0);
end if;
if alt1 = '0' then
alt1 := '1';
else
pr_state <= fill_ram;
end if;
end if;
END CASE;
END IF;
END IF;
END PROCESS Main;
end Behavioral;```

8. ## Re: Initializing a very long vector with some repetition

Originally Posted by rafimiet
I have to initialize a very long vector in the pattern such as

What is the best way to do so? In some scenarios, it may b even bigger than this, but pattern remains similar.
Without making things more complicated, lets come to your original problem....

Why don't you use a generate statement to achieve the above(assuming x is a signal of type std_logic_vector)?

array_gen : for i in 0 to 15 generate
x(i*64 TO i*64+15) <= (others => '1');
end generate array_gen;

As Tricky mentioned in #2, it would be interesting to know what x is is!

I can't go through your long code, but...
Also I sometimes need to update the value of an object within the same loop twice, which is not possible with signals, so I use variables.
This is not good. Allow extra states (I am sure your design can live with 2 or 3 clks of extra latency), let the signals update on the next clk, and then check their values in a new state.

If you want FSM coding style from Xilinx- https://www.xilinx.com/support/docum...-pdf/lab10.pdf

•

9. ## Re: Initializing a very long vector with some repetition

This post is all very confusing, as I dont understand how the original question relates to the huge code posted.

Why don't you use a generate statement to achieve the above(assuming x is a signal of type std_logic_vector)?

array_gen : for i in 0 to 15 generate
x(i*64 TO i*64+15) <= (others => '1');
end generate array_gen;
This wont work, as this is not an initialisation, but just driving all the bits of X to constant 1. Its not clear what the OP means by initialisation - do you mean power up initialisation or initialisation as part of your running design. ie something writes all the addresses of a ram?

Please clarify exactly what the problem is.

2. With few comments, signal naming is just annoying.
3. Do you really need so many states?
4. From my brief look, it looks like an attempt to port some software. Could you not have re-architected to make it more pipeline friendly?

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