+ Post New Thread
Results 1 to 8 of 8

12th September 2017, 08:41 #1
 Join Date
 May 2015
 Posts
 37
 Helped
 0 / 0
 Points
 640
 Level
 5
shift left(or right) with arithmetic operation for data type SIGNED in VHDL
I have to use shift operation for signed data type. sll and srl are synthesizable, however sla and sra are not. How can I perform them?

12th September 2017, 08:41

12th September 2017, 09:27 #2
 Join Date
 Jun 2010
 Posts
 6,273
 Helped
 1832 / 1832
 Points
 34,223
 Level
 45
Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL
sla is the same as srl.
sra exists in the 2008 version of numeric_std (and in the '93 compatability package).
Otherwise, you can just use the resize function and slice it  or write your own
Code VHDL  [expand] 1 2 3 4 5
function "sra" (l : signed; r : natural) return signed is alias l_a : signed(l'length1 downto 0) is l; begin return resize(l_a, l_a'length + r)(l_a'length+r1 downto r); end function "sra";

12th September 2017, 09:27

12th September 2017, 09:38 #3
 Join Date
 May 2015
 Posts
 37
 Helped
 0 / 0
 Points
 640
 Level
 5
Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL
I have selected VHDL200X and the code is as follows:
Code VHDL  [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity shift is Port ( din : in STD_LOGIC_VECTOR(7 downto 0); clk : in STD_LOGIC; dout : out STD_LOGIC_VECTOR(7 downto 0)); end shift; architecture Behavioral of shift is SIGNAL s1,s2 : SIGNED(7 downto 0); begin Process(clk) VARIABLE v1 : SIGNED(7 downto 0); BEGIN IF clk'event and clk = '1' then s1 <= signed(din); s2 <= s1 sla 2; dout <= std_logic_vector(s2); END IF; END PROCESS; end Behavioral;
It shows the following error
ERROR:HDLParsers:808  Line 19. sla can not have such operands in this context.

12th September 2017, 09:38

12th September 2017, 09:52 #4
 Join Date
 Jun 2010
 Posts
 6,273
 Helped
 1832 / 1832
 Points
 34,223
 Level
 45
Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL
I assume this is Vivado? it does not support the 2008 versions of the IEEE packages. It only has selective support for some parts of VHDL 2008. Hence why they call it 200X (to cover both 2002/2008).
Afaik, Intel Quartus Pro 17 and synplify are the only two tools to have proper 2008 support
   Updated   
But like I said, you're using sla  this is identical in functionality to sll for signed. So use SLL instead.

12th September 2017, 10:07 #5
 Join Date
 May 2015
 Posts
 37
 Helped
 0 / 0
 Points
 640
 Level
 5
Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL
I assume this is Vivado?
you're using sla  this is identical in functionality to sll for signed. So use SLL instead.
x = 11001010;
y = x sll 2;
y =00101000;

12th September 2017, 10:07

12th September 2017, 10:22 #6
 Join Date
 Jun 2010
 Posts
 6,273
 Helped
 1832 / 1832
 Points
 34,223
 Level
 45
Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL
What do you expect? you're shifting it by 2 (multiplying by 4) and limiting the bit width to 8 bits, and clearly its overflowing. Shifting left always appends 0 to the right (sra and srl both do this). sra appends the sign bit.
see https://en.wikipedia.org/wiki/Arithmetic_shift

12th September 2017, 10:37 #7
 Join Date
 May 2015
 Posts
 37
 Helped
 0 / 0
 Points
 640
 Level
 5
Re: shift left(or right) with arithmetic operation for data type SIGNED in VHDL
I needed to use both sla and sra. Then I can use the function you provided above for sra and sll for sla.

12th September 2017, 10:44 #8
 Join Date
 Jun 2010
 Posts
 6,273
 Helped
 1832 / 1832
 Points
 34,223
 Level
 45
+ Post New Thread
Please login