Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] ERROR:HDLParsers:3375

Status
Not open for further replies.

rafimiet

Member level 5
Joined
May 21, 2015
Messages
94
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
2,364
I have a vhdl code, which has a line as below:
Code:
variable thrsh : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL n : INTEGER RANGE 0 TO 7 := 7;
thrsh := (n => '1', OTHERS => '0');
'n' initially is the position of MSB bit. In next iteration, it gives the position of MSB-1 bit and so on... It gives the following error:
Code:
ERROR:HDLParsers:3375 - "FSM_all.vhd" Line 439. Choices for an array aggregate (Signal 'n') must be locally static unless there is only one choice. (LRM 7.3.2.2)
As the value of 'n' keeps on changing. How can I assign it with a local value?
 
Last edited:

Yes, when assigning an aggregate like this, indexes must be integer literals or constant (Generics are not locally static either, but constants are).

The way to do it would be to do this in a process (if it isnt already and do this)


Code VHDL - [expand]
1
2
3
4
5
process(thrsh)
begin
  thrsh <= (others => '0');
  thrsh(n) <= '1';
end process;

 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top